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Commit 5ce25296 authored by anttib-5's avatar anttib-5
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bare7_1

parent 0843f9e9
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......@@ -125,11 +125,12 @@ fn main() -> ! {
//
// rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze();
//
// ** your answer here **
// The maximum frequency of pclk1 is 42MHz, and it needs to be the same frequency as the system clock.
// Which it is not since it is set to 16MHz
//
// rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();
//
// ** your answer here **
// Here is the same reason, the sysclk is only different.
//
// Commit your answers (bare7_1)
//
......
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