From 5ce25296e6056ac6dc660b16e872cddafee7ff4b Mon Sep 17 00:00:00 2001
From: anttib-5 <anttib-5@student.ltu.se>
Date: Sun, 10 Mar 2019 13:36:09 +0100
Subject: [PATCH] bare7_1
---
examples/bare7.rs | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/examples/bare7.rs b/examples/bare7.rs
index ecf0fbb..5c3ece8 100644
--- a/examples/bare7.rs
+++ b/examples/bare7.rs
@@ -125,11 +125,12 @@ fn main() -> ! {
//
// rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze();
//
-// ** your answer here **
+// The maximum frequency of pclk1 is 42MHz, and it needs to be the same frequency as the system clock.
+// Which it is not since it is set to 16MHz
//
// rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();
//
-// ** your answer here **
+// Here is the same reason, the sysclk is only different.
//
// Commit your answers (bare7_1)
//
--
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