diff --git a/examples/bare7.rs b/examples/bare7.rs
index ecf0fbb104a9443c9c469e8e5f985c6bb620f338..5c3ece8d7bbb9478ac11031344c4ec0c2520d7b5 100644
--- a/examples/bare7.rs
+++ b/examples/bare7.rs
@@ -125,11 +125,12 @@ fn main() -> ! {
 //
 //    rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze();
 //
-//    ** your answer here **
+//    The maximum frequency of pclk1 is 42MHz, and it needs to be the same frequency as the system clock.
+//    Which it is not since it is set to 16MHz
 //
 //    rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();
 //
-//    ** your answer here **
+//    Here is the same reason, the sysclk is only different.
 //
 //    Commit your answers (bare7_1)
 //