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Commit d4e09f74 authored by Henrik Theolin's avatar Henrik Theolin
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bare7_1

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......@@ -125,11 +125,11 @@ fn main() -> ! {
//
// rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze();
//
// ** your answer here **
// ** Max frequency of PCLK1 is 50 MHz **
//
// rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();
//
// ** your answer here **
// ** Using prescales there is no way of dividing 84 to reach the wanted value of 64 for PCLK2 **
//
// Commit your answers (bare7_1)
//
......
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