diff --git a/examples/bare7.rs b/examples/bare7.rs
index ecf0fbb104a9443c9c469e8e5f985c6bb620f338..48e43c731563814f8e87f30f94b53599e5eaa948 100644
--- a/examples/bare7.rs
+++ b/examples/bare7.rs
@@ -125,11 +125,11 @@ fn main() -> ! {
 //
 //    rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze();
 //
-//    ** your answer here **
+//    ** Max frequency of PCLK1 is 50 MHz **
 //
 //    rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();
 //
-//    ** your answer here **
+//    ** Using prescales there is no way of dividing 84 to reach the wanted value of 64 for PCLK2 **
 //
 //    Commit your answers (bare7_1)
 //