From d4e09f746c13b216da5faa0955f30198ca236cbd Mon Sep 17 00:00:00 2001
From: "henthe-5@student.ltu.se" <henthe-5@student.ltu.se>
Date: Wed, 6 Mar 2019 08:50:05 +0100
Subject: [PATCH] bare7_1
---
examples/bare7.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/examples/bare7.rs b/examples/bare7.rs
index ecf0fbb..48e43c7 100644
--- a/examples/bare7.rs
+++ b/examples/bare7.rs
@@ -125,11 +125,11 @@ fn main() -> ! {
//
// rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze();
//
-// ** your answer here **
+// ** Max frequency of PCLK1 is 50 MHz **
//
// rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();
//
-// ** your answer here **
+// ** Using prescales there is no way of dividing 84 to reach the wanted value of 64 for PCLK2 **
//
// Commit your answers (bare7_1)
//
--
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