bare7_1

examples/bare7.rs

@@ -125,11 +125,12 @@ fn main() -> ! {
 //
 //    rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze();
 //
-//    ** your answer here **
+//    ** PCLK1 must be lower than 42 MHz. **
 //
 //    rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();
 //
-//    ** your answer here **
+//    ** With sysclk at 84 MHz, it is impossible to get PCLK2 at 64 MHz with only a
+//    prescaler that divides by integer values. Closest PCLK2 are 84 MHz and 42 MHz. **
 //
 //    Commit your answers (bare7_1)
 //