From 075c93c19ba2d4d54845138aa965e433bc785bba Mon Sep 17 00:00:00 2001
From: sheepwall <a.sve@live.se>
Date: Sun, 10 Mar 2019 08:34:42 +0100
Subject: [PATCH] bare7_1
---
examples/bare7.rs | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/examples/bare7.rs b/examples/bare7.rs
index ecf0fbb..f69c655 100644
--- a/examples/bare7.rs
+++ b/examples/bare7.rs
@@ -125,11 +125,12 @@ fn main() -> ! {
//
// rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze();
//
-// ** your answer here **
+// ** PCLK1 must be lower than 42 MHz. **
//
// rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();
//
-// ** your answer here **
+// ** With sysclk at 84 MHz, it is impossible to get PCLK2 at 64 MHz with only a
+// prescaler that divides by integer values. Closest PCLK2 are 84 MHz and 42 MHz. **
//
// Commit your answers (bare7_1)
//
--
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