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Commit e50ae4c2 authored by Nikhil Kalige's avatar Nikhil Kalige Committed by GitHub
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Fix PWM generation for TIM1

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src/pwm.rs
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...@@ -128,6 +128,8 @@ impl<'a> Pwm<'a, TIM1> { ...@@ -128,6 +128,8 @@ impl<'a> Pwm<'a, TIM1> {
.clear_bit() .clear_bit()
}); });
tim1.bdtr.modify(|_, w| w.moe().set_bit());
self._set_period(period); self._set_period(period);
tim1.cr1.write(|w| unsafe { tim1.cr1.write(|w| unsafe {
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