From e50ae4c291ca24f3fae83adb2ff1f9f604999f36 Mon Sep 17 00:00:00 2001
From: Nikhil Kalige <nikhilkalige@users.noreply.github.com>
Date: Tue, 12 Sep 2017 00:30:53 -0700
Subject: [PATCH] Fix PWM generation for TIM1
---
src/pwm.rs | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/pwm.rs b/src/pwm.rs
index 05c0145..03aa1ed 100644
--- a/src/pwm.rs
+++ b/src/pwm.rs
@@ -127,6 +127,8 @@ impl<'a> Pwm<'a, TIM1> {
.cc4p()
.clear_bit()
});
+
+ tim1.bdtr.modify(|_, w| w.moe().set_bit());
self._set_period(period);
--
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