Auto merge of #25 - nikhilkalige:patch-1, r=japaric

Fix PWM generation for TIM1

`MOE` bit in `BDTR` register needs to be set.

src/pwm.rs

@@ -128,6 +128,8 @@ impl<'a> Pwm<'a, TIM1> {
                 .clear_bit()
         });
         
+        tim1.bdtr.modify(|_, w| w.moe().set_bit());
+
         self._set_period(period);
 
         tim1.cr1.write(|w| unsafe {