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Commit a8962d44 authored by Jorge Aparicio's avatar Jorge Aparicio
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fixes and make sure the whole documentation is visible on docs.rs

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...@@ -24,6 +24,8 @@ mod macros; ...@@ -24,6 +24,8 @@ mod macros;
pub mod asm; pub mod asm;
pub mod exception; pub mod exception;
pub mod interrupt; pub mod interrupt;
// NOTE(target_arch) is for documentation purposes
#[cfg(any(armv7m, target_arch = "x86_64"))]
pub mod itm; pub mod itm;
pub mod peripheral; pub mod peripheral;
pub mod register; pub mod register;
//! Cache and branch predictor maintenance operations //! Cache and branch predictor maintenance operations
//!
//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
use volatile_register::WO; use volatile_register::WO;
......
//! CPUID //! CPUID
use volatile_register::RO; use volatile_register::RO;
#[cfg(any(armv7m, test))] #[cfg(any(armv7m, target_arch = "x86_64"))]
use volatile_register::RW; use volatile_register::RW;
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
use peripheral::CPUID; use peripheral::CPUID;
/// Register block /// Register block
...@@ -25,21 +25,21 @@ pub struct RegisterBlock { ...@@ -25,21 +25,21 @@ pub struct RegisterBlock {
pub isar: [RO<u32>; 5], pub isar: [RO<u32>; 5],
reserved1: u32, reserved1: u32,
/// Cache Level ID /// Cache Level ID
#[cfg(any(armv7m, test))] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub clidr: RO<u32>, pub clidr: RO<u32>,
/// Cache Type /// Cache Type
#[cfg(any(armv7m, test))] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub ctr: RO<u32>, pub ctr: RO<u32>,
/// Cache Size ID /// Cache Size ID
#[cfg(any(armv7m, test))] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub ccsidr: RO<u32>, pub ccsidr: RO<u32>,
/// Cache Size Selection /// Cache Size Selection
#[cfg(any(armv7m, test))] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub csselr: RW<u32>, pub csselr: RW<u32>,
} }
/// Type of cache to select on CSSELR writes. /// Type of cache to select on CSSELR writes.
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub enum CsselrCacheType { pub enum CsselrCacheType {
/// Select DCache or unified cache /// Select DCache or unified cache
DataOrUnified = 0, DataOrUnified = 0,
...@@ -47,7 +47,7 @@ pub enum CsselrCacheType { ...@@ -47,7 +47,7 @@ pub enum CsselrCacheType {
Instruction = 1, Instruction = 1,
} }
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl CPUID { impl CPUID {
/// Selects the current CCSIDR /// Selects the current CCSIDR
/// ///
......
//! Flash Patch and Breakpoint unit //! Flash Patch and Breakpoint unit
//!
//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
use volatile_register::{RO, RW, WO}; use volatile_register::{RO, RW, WO};
......
//! Floating Point Unit //! Floating Point Unit
//!
//! *NOTE* Available only on ARMv7E-M (`thumbv7em-none-eabihf`)
use volatile_register::{RO, RW}; use volatile_register::{RO, RW};
......
//! Instrumentation Trace Macrocell //! Instrumentation Trace Macrocell
//!
//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
use core::cell::UnsafeCell; use core::cell::UnsafeCell;
use core::ptr; use core::ptr;
......
...@@ -70,26 +70,27 @@ ...@@ -70,26 +70,27 @@
#![allow(private_no_mangle_statics)] #![allow(private_no_mangle_statics)]
use core::marker::PhantomData; use core::marker::PhantomData;
use core::ops::{Deref, DerefMut}; use core::ops;
use interrupt; use interrupt;
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub mod cbp; pub mod cbp;
pub mod cpuid; pub mod cpuid;
pub mod dcb; pub mod dcb;
pub mod dwt; pub mod dwt;
#[cfg(any(armv7m, test))] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub mod fpb; pub mod fpb;
#[cfg(any(has_fpu, test))] #[cfg(any(has_fpu, target_arch = "x86_64"))]
pub mod fpu; pub mod fpu;
#[cfg(any(armv7m, test))] // NOTE(target_arch) is for documentation purposes
#[cfg(any(armv7m, target_arch = "x86_64"))]
pub mod itm; pub mod itm;
pub mod mpu; pub mod mpu;
pub mod nvic; pub mod nvic;
pub mod scb; pub mod scb;
pub mod syst; pub mod syst;
#[cfg(any(armv7m, test))] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub mod tpiu; pub mod tpiu;
#[cfg(test)] #[cfg(test)]
...@@ -101,7 +102,7 @@ mod test; ...@@ -101,7 +102,7 @@ mod test;
#[allow(non_snake_case)] #[allow(non_snake_case)]
pub struct Peripherals { pub struct Peripherals {
/// Cache and branch predictor maintenance operations /// Cache and branch predictor maintenance operations
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub CBP: CBP, pub CBP: CBP,
/// CPUID /// CPUID
pub CPUID: CPUID, pub CPUID: CPUID,
...@@ -110,13 +111,13 @@ pub struct Peripherals { ...@@ -110,13 +111,13 @@ pub struct Peripherals {
/// Data Watchpoint and Trace unit /// Data Watchpoint and Trace unit
pub DWT: DWT, pub DWT: DWT,
/// Flash Patch and Breakpoint unit /// Flash Patch and Breakpoint unit
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub FPB: FPB, pub FPB: FPB,
/// Floating Point Unit /// Floating Point Unit
#[cfg(has_fpu)] #[cfg(any(has_fpu, target_arch = "x86_64"))]
pub FPU: FPU, pub FPU: FPU,
/// Instrumentation Trace Macrocell /// Instrumentation Trace Macrocell
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub ITM: ITM, pub ITM: ITM,
/// Memory Protection Unit /// Memory Protection Unit
pub MPU: MPU, pub MPU: MPU,
...@@ -127,7 +128,7 @@ pub struct Peripherals { ...@@ -127,7 +128,7 @@ pub struct Peripherals {
/// SysTick: System Timer /// SysTick: System Timer
pub SYST: SYST, pub SYST: SYST,
/// Trace Port Interface Unit; /// Trace Port Interface Unit;
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
pub TPIU: TPIU, pub TPIU: TPIU,
} }
...@@ -156,7 +157,7 @@ impl Peripherals { ...@@ -156,7 +157,7 @@ impl Peripherals {
CORE_PERIPHERALS = true; CORE_PERIPHERALS = true;
Peripherals { Peripherals {
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
CBP: CBP { CBP: CBP {
_marker: PhantomData, _marker: PhantomData,
}, },
...@@ -169,15 +170,15 @@ impl Peripherals { ...@@ -169,15 +170,15 @@ impl Peripherals {
DWT: DWT { DWT: DWT {
_marker: PhantomData, _marker: PhantomData,
}, },
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
FPB: FPB { FPB: FPB {
_marker: PhantomData, _marker: PhantomData,
}, },
#[cfg(has_fpu)] #[cfg(any(has_fpu, target_arch = "x86_64"))]
FPU: FPU { FPU: FPU {
_marker: PhantomData, _marker: PhantomData,
}, },
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
ITM: ITM { ITM: ITM {
_marker: PhantomData, _marker: PhantomData,
}, },
...@@ -193,7 +194,7 @@ impl Peripherals { ...@@ -193,7 +194,7 @@ impl Peripherals {
SYST: SYST { SYST: SYST {
_marker: PhantomData, _marker: PhantomData,
}, },
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
TPIU: TPIU { TPIU: TPIU {
_marker: PhantomData, _marker: PhantomData,
}, },
...@@ -202,12 +203,14 @@ impl Peripherals { ...@@ -202,12 +203,14 @@ impl Peripherals {
} }
/// Cache and branch predictor maintenance operations /// Cache and branch predictor maintenance operations
#[cfg(armv7m)] ///
/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
#[cfg(any(armv7m, target_arch = "x86_64"))]
pub struct CBP { pub struct CBP {
_marker: PhantomData<*const ()>, _marker: PhantomData<*const ()>,
} }
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl CBP { impl CBP {
pub(crate) unsafe fn new() -> Self { pub(crate) unsafe fn new() -> Self {
CBP { CBP {
...@@ -221,11 +224,11 @@ impl CBP { ...@@ -221,11 +224,11 @@ impl CBP {
} }
} }
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
unsafe impl Send for CBP {} unsafe impl Send for CBP {}
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl Deref for CBP { impl ops::Deref for CBP {
type Target = self::cbp::RegisterBlock; type Target = self::cbp::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -245,7 +248,7 @@ impl CPUID { ...@@ -245,7 +248,7 @@ impl CPUID {
} }
} }
impl Deref for CPUID { impl ops::Deref for CPUID {
type Target = self::cpuid::RegisterBlock; type Target = self::cpuid::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -265,7 +268,7 @@ impl DCB { ...@@ -265,7 +268,7 @@ impl DCB {
} }
} }
impl Deref for DCB { impl ops::Deref for DCB {
type Target = self::dcb::RegisterBlock; type Target = self::dcb::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -285,7 +288,7 @@ impl DWT { ...@@ -285,7 +288,7 @@ impl DWT {
} }
} }
impl Deref for DWT { impl ops::Deref for DWT {
type Target = self::dwt::RegisterBlock; type Target = self::dwt::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -294,12 +297,14 @@ impl Deref for DWT { ...@@ -294,12 +297,14 @@ impl Deref for DWT {
} }
/// Flash Patch and Breakpoint unit /// Flash Patch and Breakpoint unit
#[cfg(any(armv7m, test))] ///
/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
#[cfg(any(armv7m, target_arch = "x86_64"))]
pub struct FPB { pub struct FPB {
_marker: PhantomData<*const ()>, _marker: PhantomData<*const ()>,
} }
#[cfg(any(armv7m, test))] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl FPB { impl FPB {
/// Returns a pointer to the register block /// Returns a pointer to the register block
pub fn ptr() -> *const fpb::RegisterBlock { pub fn ptr() -> *const fpb::RegisterBlock {
...@@ -307,8 +312,8 @@ impl FPB { ...@@ -307,8 +312,8 @@ impl FPB {
} }
} }
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl Deref for FPB { impl ops::Deref for FPB {
type Target = self::fpb::RegisterBlock; type Target = self::fpb::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -317,12 +322,14 @@ impl Deref for FPB { ...@@ -317,12 +322,14 @@ impl Deref for FPB {
} }
/// Floating Point Unit /// Floating Point Unit
#[cfg(any(has_fpu, test))] ///
/// *NOTE* Available only on ARMv7E-M (`thumbv7em-none-eabihf`)
#[cfg(any(has_fpu, target_arch = "x86_64"))]
pub struct FPU { pub struct FPU {
_marker: PhantomData<*const ()>, _marker: PhantomData<*const ()>,
} }
#[cfg(any(has_fpu, test))] #[cfg(any(has_fpu, target_arch = "x86_64"))]
impl FPU { impl FPU {
/// Returns a pointer to the register block /// Returns a pointer to the register block
pub fn ptr() -> *const fpu::RegisterBlock { pub fn ptr() -> *const fpu::RegisterBlock {
...@@ -330,8 +337,8 @@ impl FPU { ...@@ -330,8 +337,8 @@ impl FPU {
} }
} }
#[cfg(has_fpu)] #[cfg(any(has_fpu, target_arch = "x86_64"))]
impl Deref for FPU { impl ops::Deref for FPU {
type Target = self::fpu::RegisterBlock; type Target = self::fpu::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -340,12 +347,14 @@ impl Deref for FPU { ...@@ -340,12 +347,14 @@ impl Deref for FPU {
} }
/// Instrumentation Trace Macrocell /// Instrumentation Trace Macrocell
#[cfg(any(armv7m, test))] ///
/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
#[cfg(any(armv7m, target_arch = "x86_64"))]
pub struct ITM { pub struct ITM {
_marker: PhantomData<*const ()>, _marker: PhantomData<*const ()>,
} }
#[cfg(any(armv7m, test))] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl ITM { impl ITM {
/// Returns a pointer to the register block /// Returns a pointer to the register block
pub fn ptr() -> *mut itm::RegisterBlock { pub fn ptr() -> *mut itm::RegisterBlock {
...@@ -353,8 +362,8 @@ impl ITM { ...@@ -353,8 +362,8 @@ impl ITM {
} }
} }
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl Deref for ITM { impl ops::Deref for ITM {
type Target = self::itm::RegisterBlock; type Target = self::itm::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -362,8 +371,8 @@ impl Deref for ITM { ...@@ -362,8 +371,8 @@ impl Deref for ITM {
} }
} }
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl DerefMut for ITM { impl ops::DerefMut for ITM {
fn deref_mut(&mut self) -> &mut Self::Target { fn deref_mut(&mut self) -> &mut Self::Target {
unsafe { &mut *Self::ptr() } unsafe { &mut *Self::ptr() }
} }
...@@ -381,7 +390,7 @@ impl MPU { ...@@ -381,7 +390,7 @@ impl MPU {
} }
} }
impl Deref for MPU { impl ops::Deref for MPU {
type Target = self::mpu::RegisterBlock; type Target = self::mpu::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -401,7 +410,7 @@ impl NVIC { ...@@ -401,7 +410,7 @@ impl NVIC {
} }
} }
impl Deref for NVIC { impl ops::Deref for NVIC {
type Target = self::nvic::RegisterBlock; type Target = self::nvic::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -421,7 +430,7 @@ impl SCB { ...@@ -421,7 +430,7 @@ impl SCB {
} }
} }
impl Deref for SCB { impl ops::Deref for SCB {
type Target = self::scb::RegisterBlock; type Target = self::scb::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -441,7 +450,7 @@ impl SYST { ...@@ -441,7 +450,7 @@ impl SYST {
} }
} }
impl Deref for SYST { impl ops::Deref for SYST {
type Target = self::syst::RegisterBlock; type Target = self::syst::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
...@@ -450,12 +459,14 @@ impl Deref for SYST { ...@@ -450,12 +459,14 @@ impl Deref for SYST {
} }
/// Trace Port Interface Unit; /// Trace Port Interface Unit;
#[cfg(any(armv7m, test))] ///
/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
#[cfg(any(armv7m, target_arch = "x86_64"))]
pub struct TPIU { pub struct TPIU {
_marker: PhantomData<*const ()>, _marker: PhantomData<*const ()>,
} }
#[cfg(any(armv7m, test))] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl TPIU { impl TPIU {
/// Returns a pointer to the register block /// Returns a pointer to the register block
pub fn ptr() -> *const tpiu::RegisterBlock { pub fn ptr() -> *const tpiu::RegisterBlock {
...@@ -463,8 +474,8 @@ impl TPIU { ...@@ -463,8 +474,8 @@ impl TPIU {
} }
} }
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl Deref for TPIU { impl ops::Deref for TPIU {
type Target = self::tpiu::RegisterBlock; type Target = self::tpiu::RegisterBlock;
fn deref(&self) -> &Self::Target { fn deref(&self) -> &Self::Target {
......
...@@ -2,11 +2,11 @@ ...@@ -2,11 +2,11 @@
use volatile_register::RW; use volatile_register::RW;
#[cfg(any(armv7m, has_fpu))] #[cfg(any(armv7m, has_fpu, target_arch = "x86_64"))]
use super::{CBP, SCB}; use super::{CBP, SCB};
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
use super::CPUID; use super::CPUID;
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
use super::cpuid::CsselrCacheType; use super::cpuid::CsselrCacheType;
/// Register block /// Register block
...@@ -108,16 +108,16 @@ impl SCB { ...@@ -108,16 +108,16 @@ impl SCB {
} }
} }
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
mod scb_consts { mod scb_consts {
pub const SCB_CCR_IC_MASK: u32 = (1 << 17); pub const SCB_CCR_IC_MASK: u32 = (1 << 17);
pub const SCB_CCR_DC_MASK: u32 = (1 << 16); pub const SCB_CCR_DC_MASK: u32 = (1 << 16);
} }
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
use self::scb_consts::*; use self::scb_consts::*;
#[cfg(armv7m)] #[cfg(any(armv7m, target_arch = "x86_64"))]
impl SCB { impl SCB {
/// Enables I-Cache if currently disabled /// Enables I-Cache if currently disabled
#[inline] #[inline]
......
//! Trace Port Interface Unit; //! Trace Port Interface Unit;
//!
//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
use volatile_register::{RO, RW, WO}; use volatile_register::{RO, RW, WO};
......
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