diff --git a/src/lib.rs b/src/lib.rs
index aabd189e2f8ea7f8b643caa63159073978af9ff1..9c00ceac6cd42f4f6ff5a5202ac6ecfceb11d24d 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -24,6 +24,8 @@ mod macros;
pub mod asm;
pub mod exception;
pub mod interrupt;
+// NOTE(target_arch) is for documentation purposes
+#[cfg(any(armv7m, target_arch = "x86_64"))]
pub mod itm;
pub mod peripheral;
pub mod register;
diff --git a/src/peripheral/cbp.rs b/src/peripheral/cbp.rs
index 590cb7be34a57d9310f70a057fe921b9298c607e..2535d0bd8e63b8f45b4491a3f9ac43692a0332b9 100644
--- a/src/peripheral/cbp.rs
+++ b/src/peripheral/cbp.rs
@@ -1,4 +1,6 @@
//! Cache and branch predictor maintenance operations
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
use volatile_register::WO;
diff --git a/src/peripheral/cpuid.rs b/src/peripheral/cpuid.rs
index 624d5c58bff30eab6b95344cf95a1004b185b7d8..94a2c2027226e88cac384cf01fac5543d636c1cc 100644
--- a/src/peripheral/cpuid.rs
+++ b/src/peripheral/cpuid.rs
@@ -1,10 +1,10 @@
//! CPUID
use volatile_register::RO;
-#[cfg(any(armv7m, test))]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
use volatile_register::RW;
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
use peripheral::CPUID;
/// Register block
@@ -25,21 +25,21 @@ pub struct RegisterBlock {
pub isar: [RO<u32>; 5],
reserved1: u32,
/// Cache Level ID
- #[cfg(any(armv7m, test))]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
pub clidr: RO<u32>,
/// Cache Type
- #[cfg(any(armv7m, test))]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
pub ctr: RO<u32>,
/// Cache Size ID
- #[cfg(any(armv7m, test))]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
pub ccsidr: RO<u32>,
/// Cache Size Selection
- #[cfg(any(armv7m, test))]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
pub csselr: RW<u32>,
}
/// Type of cache to select on CSSELR writes.
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
pub enum CsselrCacheType {
/// Select DCache or unified cache
DataOrUnified = 0,
@@ -47,7 +47,7 @@ pub enum CsselrCacheType {
Instruction = 1,
}
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
impl CPUID {
/// Selects the current CCSIDR
///
diff --git a/src/peripheral/fpb.rs b/src/peripheral/fpb.rs
index 0da2d5d12506f6a05f6773998ee3e3e5d00467af..215d4ff9dbe5937646ec661358bc57ed679b2ed3 100644
--- a/src/peripheral/fpb.rs
+++ b/src/peripheral/fpb.rs
@@ -1,4 +1,6 @@
//! Flash Patch and Breakpoint unit
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
use volatile_register::{RO, RW, WO};
diff --git a/src/peripheral/fpu.rs b/src/peripheral/fpu.rs
index f1d47539946dba483abeb7c5bae5d9d9b1cd72f7..c4e8a1d2439a9dcd5b352ca953800c1e0dd20286 100644
--- a/src/peripheral/fpu.rs
+++ b/src/peripheral/fpu.rs
@@ -1,4 +1,6 @@
//! Floating Point Unit
+//!
+//! *NOTE* Available only on ARMv7E-M (`thumbv7em-none-eabihf`)
use volatile_register::{RO, RW};
diff --git a/src/peripheral/itm.rs b/src/peripheral/itm.rs
index fd4a2fd04e7e06ff06aaa769bf80a4fef4a70d9e..b424817a811d546ac0ea80bb7a7e236368f7d288 100644
--- a/src/peripheral/itm.rs
+++ b/src/peripheral/itm.rs
@@ -1,4 +1,6 @@
//! Instrumentation Trace Macrocell
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
use core::cell::UnsafeCell;
use core::ptr;
diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index 67bcb21fae3a1e90defb641a428f750682b462a4..2abe79f62c3606d129ef4998d85906900a72b577 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -70,26 +70,27 @@
#![allow(private_no_mangle_statics)]
use core::marker::PhantomData;
-use core::ops::{Deref, DerefMut};
+use core::ops;
use interrupt;
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
pub mod cbp;
pub mod cpuid;
pub mod dcb;
pub mod dwt;
-#[cfg(any(armv7m, test))]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
pub mod fpb;
-#[cfg(any(has_fpu, test))]
+#[cfg(any(has_fpu, target_arch = "x86_64"))]
pub mod fpu;
-#[cfg(any(armv7m, test))]
+// NOTE(target_arch) is for documentation purposes
+#[cfg(any(armv7m, target_arch = "x86_64"))]
pub mod itm;
pub mod mpu;
pub mod nvic;
pub mod scb;
pub mod syst;
-#[cfg(any(armv7m, test))]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
pub mod tpiu;
#[cfg(test)]
@@ -101,7 +102,7 @@ mod test;
#[allow(non_snake_case)]
pub struct Peripherals {
/// Cache and branch predictor maintenance operations
- #[cfg(armv7m)]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
pub CBP: CBP,
/// CPUID
pub CPUID: CPUID,
@@ -110,13 +111,13 @@ pub struct Peripherals {
/// Data Watchpoint and Trace unit
pub DWT: DWT,
/// Flash Patch and Breakpoint unit
- #[cfg(armv7m)]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
pub FPB: FPB,
/// Floating Point Unit
- #[cfg(has_fpu)]
+ #[cfg(any(has_fpu, target_arch = "x86_64"))]
pub FPU: FPU,
/// Instrumentation Trace Macrocell
- #[cfg(armv7m)]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
pub ITM: ITM,
/// Memory Protection Unit
pub MPU: MPU,
@@ -127,7 +128,7 @@ pub struct Peripherals {
/// SysTick: System Timer
pub SYST: SYST,
/// Trace Port Interface Unit;
- #[cfg(armv7m)]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
pub TPIU: TPIU,
}
@@ -156,7 +157,7 @@ impl Peripherals {
CORE_PERIPHERALS = true;
Peripherals {
- #[cfg(armv7m)]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
CBP: CBP {
_marker: PhantomData,
},
@@ -169,15 +170,15 @@ impl Peripherals {
DWT: DWT {
_marker: PhantomData,
},
- #[cfg(armv7m)]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
FPB: FPB {
_marker: PhantomData,
},
- #[cfg(has_fpu)]
+ #[cfg(any(has_fpu, target_arch = "x86_64"))]
FPU: FPU {
_marker: PhantomData,
},
- #[cfg(armv7m)]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
ITM: ITM {
_marker: PhantomData,
},
@@ -193,7 +194,7 @@ impl Peripherals {
SYST: SYST {
_marker: PhantomData,
},
- #[cfg(armv7m)]
+ #[cfg(any(armv7m, target_arch = "x86_64"))]
TPIU: TPIU {
_marker: PhantomData,
},
@@ -202,12 +203,14 @@ impl Peripherals {
}
/// Cache and branch predictor maintenance operations
-#[cfg(armv7m)]
+///
+/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+#[cfg(any(armv7m, target_arch = "x86_64"))]
pub struct CBP {
_marker: PhantomData<*const ()>,
}
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
impl CBP {
pub(crate) unsafe fn new() -> Self {
CBP {
@@ -221,11 +224,11 @@ impl CBP {
}
}
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
unsafe impl Send for CBP {}
-#[cfg(armv7m)]
-impl Deref for CBP {
+#[cfg(any(armv7m, target_arch = "x86_64"))]
+impl ops::Deref for CBP {
type Target = self::cbp::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -245,7 +248,7 @@ impl CPUID {
}
}
-impl Deref for CPUID {
+impl ops::Deref for CPUID {
type Target = self::cpuid::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -265,7 +268,7 @@ impl DCB {
}
}
-impl Deref for DCB {
+impl ops::Deref for DCB {
type Target = self::dcb::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -285,7 +288,7 @@ impl DWT {
}
}
-impl Deref for DWT {
+impl ops::Deref for DWT {
type Target = self::dwt::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -294,12 +297,14 @@ impl Deref for DWT {
}
/// Flash Patch and Breakpoint unit
-#[cfg(any(armv7m, test))]
+///
+/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+#[cfg(any(armv7m, target_arch = "x86_64"))]
pub struct FPB {
_marker: PhantomData<*const ()>,
}
-#[cfg(any(armv7m, test))]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
impl FPB {
/// Returns a pointer to the register block
pub fn ptr() -> *const fpb::RegisterBlock {
@@ -307,8 +312,8 @@ impl FPB {
}
}
-#[cfg(armv7m)]
-impl Deref for FPB {
+#[cfg(any(armv7m, target_arch = "x86_64"))]
+impl ops::Deref for FPB {
type Target = self::fpb::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -317,12 +322,14 @@ impl Deref for FPB {
}
/// Floating Point Unit
-#[cfg(any(has_fpu, test))]
+///
+/// *NOTE* Available only on ARMv7E-M (`thumbv7em-none-eabihf`)
+#[cfg(any(has_fpu, target_arch = "x86_64"))]
pub struct FPU {
_marker: PhantomData<*const ()>,
}
-#[cfg(any(has_fpu, test))]
+#[cfg(any(has_fpu, target_arch = "x86_64"))]
impl FPU {
/// Returns a pointer to the register block
pub fn ptr() -> *const fpu::RegisterBlock {
@@ -330,8 +337,8 @@ impl FPU {
}
}
-#[cfg(has_fpu)]
-impl Deref for FPU {
+#[cfg(any(has_fpu, target_arch = "x86_64"))]
+impl ops::Deref for FPU {
type Target = self::fpu::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -340,12 +347,14 @@ impl Deref for FPU {
}
/// Instrumentation Trace Macrocell
-#[cfg(any(armv7m, test))]
+///
+/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+#[cfg(any(armv7m, target_arch = "x86_64"))]
pub struct ITM {
_marker: PhantomData<*const ()>,
}
-#[cfg(any(armv7m, test))]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
impl ITM {
/// Returns a pointer to the register block
pub fn ptr() -> *mut itm::RegisterBlock {
@@ -353,8 +362,8 @@ impl ITM {
}
}
-#[cfg(armv7m)]
-impl Deref for ITM {
+#[cfg(any(armv7m, target_arch = "x86_64"))]
+impl ops::Deref for ITM {
type Target = self::itm::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -362,8 +371,8 @@ impl Deref for ITM {
}
}
-#[cfg(armv7m)]
-impl DerefMut for ITM {
+#[cfg(any(armv7m, target_arch = "x86_64"))]
+impl ops::DerefMut for ITM {
fn deref_mut(&mut self) -> &mut Self::Target {
unsafe { &mut *Self::ptr() }
}
@@ -381,7 +390,7 @@ impl MPU {
}
}
-impl Deref for MPU {
+impl ops::Deref for MPU {
type Target = self::mpu::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -401,7 +410,7 @@ impl NVIC {
}
}
-impl Deref for NVIC {
+impl ops::Deref for NVIC {
type Target = self::nvic::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -421,7 +430,7 @@ impl SCB {
}
}
-impl Deref for SCB {
+impl ops::Deref for SCB {
type Target = self::scb::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -441,7 +450,7 @@ impl SYST {
}
}
-impl Deref for SYST {
+impl ops::Deref for SYST {
type Target = self::syst::RegisterBlock;
fn deref(&self) -> &Self::Target {
@@ -450,12 +459,14 @@ impl Deref for SYST {
}
/// Trace Port Interface Unit;
-#[cfg(any(armv7m, test))]
+///
+/// *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
+#[cfg(any(armv7m, target_arch = "x86_64"))]
pub struct TPIU {
_marker: PhantomData<*const ()>,
}
-#[cfg(any(armv7m, test))]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
impl TPIU {
/// Returns a pointer to the register block
pub fn ptr() -> *const tpiu::RegisterBlock {
@@ -463,8 +474,8 @@ impl TPIU {
}
}
-#[cfg(armv7m)]
-impl Deref for TPIU {
+#[cfg(any(armv7m, target_arch = "x86_64"))]
+impl ops::Deref for TPIU {
type Target = self::tpiu::RegisterBlock;
fn deref(&self) -> &Self::Target {
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs
index 9a922c76700ae0be4d38a7e99d9d3e344026802a..41f38253d4e13b9605b09bcdd19a13ab3ec6da0d 100644
--- a/src/peripheral/scb.rs
+++ b/src/peripheral/scb.rs
@@ -2,11 +2,11 @@
use volatile_register::RW;
-#[cfg(any(armv7m, has_fpu))]
+#[cfg(any(armv7m, has_fpu, target_arch = "x86_64"))]
use super::{CBP, SCB};
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
use super::CPUID;
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
use super::cpuid::CsselrCacheType;
/// Register block
@@ -108,16 +108,16 @@ impl SCB {
}
}
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
mod scb_consts {
pub const SCB_CCR_IC_MASK: u32 = (1 << 17);
pub const SCB_CCR_DC_MASK: u32 = (1 << 16);
}
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
use self::scb_consts::*;
-#[cfg(armv7m)]
+#[cfg(any(armv7m, target_arch = "x86_64"))]
impl SCB {
/// Enables I-Cache if currently disabled
#[inline]
diff --git a/src/peripheral/tpiu.rs b/src/peripheral/tpiu.rs
index 7a08805faa8cad0eac2fc758e30735cef779f052..4115bb32094892ec2ae337d7b458682a63b9b440 100644
--- a/src/peripheral/tpiu.rs
+++ b/src/peripheral/tpiu.rs
@@ -1,4 +1,6 @@
//! Trace Port Interface Unit;
+//!
+//! *NOTE* Available only on ARMv7-M (`thumbv7*m-none-eabi*`)
use volatile_register::{RO, RW, WO};