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Carl Österberg
e7020e_2021
Commits
2f533b1a
Commit
2f533b1a
authored
4 years ago
by
Carl Österberg
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bare6_7
parent
5e1feb41
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2 changed files
examples/rtic_bare6.rs
+19
-12
19 additions, 12 deletions
examples/rtic_bare6.rs
pictures/bare_6_48mhz_low_speed
+0
-0
0 additions, 0 deletions
pictures/bare_6_48mhz_low_speed
with
19 additions
and
12 deletions
examples/rtic_bare6.rs
+
19
−
12
View file @
2f533b1a
...
@@ -59,11 +59,11 @@ const APP: () = {
...
@@ -59,11 +59,11 @@ const APP: () = {
//let _clocks = rcc.cfgr.freeze();
//let _clocks = rcc.cfgr.freeze();
//Set up the system clock. 48 MHz?
//Set up the system clock. 48 MHz?
let
_clocks
=
rcc
//
let _clocks = rcc
.cfgr
//
.cfgr
.sysclk
(
48
.mhz
())
//
.sysclk(48.mhz())
.pclk1
(
24
.mhz
())
//
.pclk1(24.mhz())
.freeze
();
//
.freeze();
// let _clocks = rcc
// let _clocks = rcc
// .cfgr
// .cfgr
...
@@ -72,12 +72,12 @@ const APP: () = {
...
@@ -72,12 +72,12 @@ const APP: () = {
// .pclk2(64.mhz())
// .pclk2(64.mhz())
// .freeze();
// .freeze();
//
//
//
let _clocks = rcc
let
_clocks
=
rcc
//
.cfgr
.cfgr
//
.sysclk(84.mhz())
.sysclk
(
84
.mhz
())
//
.pclk1(42.mhz())
.pclk1
(
42
.mhz
())
//
.pclk2(64.mhz())
.pclk2
(
64
.mhz
())
//
.freeze();
.freeze
();
// pass on late resources
// pass on late resources
init
::
LateResources
{
init
::
LateResources
{
...
@@ -138,7 +138,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
...
@@ -138,7 +138,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
// otyper reset state push/pull, in reset state (don't need to change)
// otyper reset state push/pull, in reset state (don't need to change)
// ospeedr 0b11 = very high speed
// ospeedr 0b11 = very high speed
gpioc
.ospeedr
.modify
(|
_
,
w
|
w
.ospeedr9
()
.
high
_speed
());
gpioc
.ospeedr
.modify
(|
_
,
w
|
w
.ospeedr9
()
.
low
_speed
());
}
}
// 0. Background reading:
// 0. Background reading:
...
@@ -343,10 +343,12 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
...
@@ -343,10 +343,12 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
// Did the frequency change in comparison to assignment 5?
// Did the frequency change in comparison to assignment 5?
//
//
// ** your answer here **
// ** your answer here **
// No
//
//
// What is the peak to peak reading of the signal (and why did it change)?
// What is the peak to peak reading of the signal (and why did it change)?
//
//
// ** your answer here **
// ** your answer here **
// 5.5V,
//
//
// Make a screen dump or photo of the oscilloscope output.
// Make a screen dump or photo of the oscilloscope output.
// Save the the picture as "bare_6_48mhz_low_speed".
// Save the the picture as "bare_6_48mhz_low_speed".
...
@@ -360,10 +362,12 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
...
@@ -360,10 +362,12 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
// Does the code compile?
// Does the code compile?
//
//
// ** your answer here **
// ** your answer here **
// No
//
//
// What happens at run-time?
// What happens at run-time?
//
//
// ** your answer here **
// ** your answer here **
// It panics beacuse we try to set pclk1 to higher then its maximum value.
//
//
// Try setting the clocks according to:
// Try setting the clocks according to:
//
//
...
@@ -372,12 +376,15 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
...
@@ -372,12 +376,15 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
// Does the code compile?
// Does the code compile?
//
//
// ** your answer here **
// ** your answer here **
// yes
//
//
// What happens at run-time?
// What happens at run-time?
//
//
// ** your answer here **
// ** your answer here **
// It sets the registers and runs ?
//
//
// Is that a correct?
// Is that a correct?
// it is a correct
//
//
// Optional: If you find it incorrect, file an issue to `stm32f4xx-hal` describing the problem.
// Optional: If you find it incorrect, file an issue to `stm32f4xx-hal` describing the problem.
// (Remember always check already open issues, and add to existing if related.)
// (Remember always check already open issues, and add to existing if related.)
...
...
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