diff --git a/examples/rtic_bare6.rs b/examples/rtic_bare6.rs
index 869e7dc8009115a9ae1f548aa9ec6ce4fe89e9dd..d4743ecf608c790e3f07256aea16fa685d00413e 100644
--- a/examples/rtic_bare6.rs
+++ b/examples/rtic_bare6.rs
@@ -59,11 +59,11 @@ const APP: () = {
         //let _clocks = rcc.cfgr.freeze();
 
         //Set up the system clock. 48 MHz?
-        let _clocks = rcc
-            .cfgr
-            .sysclk(48.mhz())
-            .pclk1(24.mhz())
-            .freeze();
+        // let _clocks = rcc
+        //     .cfgr
+        //     .sysclk(48.mhz())
+        //     .pclk1(24.mhz())
+        //     .freeze();
 
         // let _clocks = rcc
         //     .cfgr
@@ -72,12 +72,12 @@ const APP: () = {
         //     .pclk2(64.mhz())
         //     .freeze();
         //
-        // let _clocks = rcc
-        //     .cfgr
-        //     .sysclk(84.mhz())
-        //     .pclk1(42.mhz())
-        //     .pclk2(64.mhz())
-        //     .freeze();
+        let _clocks = rcc
+            .cfgr
+            .sysclk(84.mhz())
+            .pclk1(42.mhz())
+            .pclk2(64.mhz())
+            .freeze();
 
         // pass on late resources
         init::LateResources {
@@ -138,7 +138,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
     // otyper reset state push/pull, in reset state (don't need to change)
 
     // ospeedr 0b11 = very high speed
-    gpioc.ospeedr.modify(|_, w| w.ospeedr9().high_speed());
+    gpioc.ospeedr.modify(|_, w| w.ospeedr9().low_speed());
 }
 
 // 0. Background reading:
@@ -343,10 +343,12 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 //    Did the frequency change in comparison to assignment 5?
 //
 //    ** your answer here **
+//    No
 //
 //    What is the peak to peak reading of the signal (and why did it change)?
 //
 //    ** your answer here **
+//    5.5V, 
 //
 //    Make a screen dump or photo of the oscilloscope output.
 //    Save the the picture as "bare_6_48mhz_low_speed".
@@ -360,10 +362,12 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 //    Does the code compile?
 //
 //    ** your answer here **
+//    No
 //
 //    What happens at run-time?
 //
 //    ** your answer here **
+//    It panics beacuse we try to set pclk1 to higher then its maximum value.
 //
 //    Try setting the clocks according to:
 //
@@ -372,12 +376,15 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 //    Does the code compile?
 //
 //    ** your answer here **
+//    yes
 //
 //    What happens at run-time?
 //
 //    ** your answer here **
+//    It sets the registers and runs ?
 //
 //    Is that a correct?
+//    it is a correct
 //
 //    Optional: If you find it incorrect, file an issue to `stm32f4xx-hal` describing the problem.
 //    (Remember always check already open issues, and add to existing if related.)
diff --git a/pictures/bare_6_48mhz_low_speed b/pictures/bare_6_48mhz_low_speed
new file mode 100644
index 0000000000000000000000000000000000000000..feb55398e08418772e0ca8f157bfd1824f66a902
Binary files /dev/null and b/pictures/bare_6_48mhz_low_speed differ