bare7_2

examples/bare6.rs

@@ -82,8 +82,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 
     // mco2 	: SYSCLK = 0b00
     // mcopre 	: divide by 4 = 0b110
-    rcc.cfgr
-        .modify(|_, w| unsafe { w.mco2().sysclk().mco2pre().div4() }); // w.mco2().bits(0b00).mco2pre().bits(0b110)
+    rcc.cfgr.modify(|_, w| w.mco2().sysclk().mco2pre().div4() ); // w.mco2().bits(0b00).mco2pre().bits(0b110)
    
     // power on GPIOC, RM0368 6.3.11
     rcc.ahb1enr.modify(|_, w| w.gpiocen().enabled() ); //

examples/bare7.rs

@@ -30,10 +30,23 @@ fn main() -> ! {
 
     let p = hal::stm32::Peripherals::take().unwrap();
 
-    let rcc = p.RCC.constrain();
 
-    // 16 MHz (default, all clocks)
-    let clocks = rcc.cfgr.freeze();
+    let rcc = p.RCC;
+
+    // Output MCO2 to PC9 as SYSCLK/4:
+    rcc.cfgr.modify(|_, w| w.mco2().sysclk().mco2pre().div4());
+
+    // Enable GPIOC:
+    rcc.ahb1enr.modify(|_, w| w.gpiocen().enabled());
+    let gpioc = p.GPIOC;
+
+    // Set Port C pin 9 to alternate function MCO2.
+    gpioc.moder.modify(|_, w| w.moder9().alternate());
+    gpioc.ospeedr.modify(|_, w| w.ospeedr9().very_high_speed());
+
+    // Now lock the clocks:
+    let rcc = rcc.constrain();
+    let clocks = rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(42.mhz()).freeze();
 
     let gpioa = p.GPIOA.split();
 
@@ -145,15 +158,15 @@ fn main() -> ! {
 //
 //    What is the frequency of MCO2 read by the oscilloscope.
 //
-//    ** your answer here **
+//    ** 21.053 MHz **
 //
 //    Compute the value of SYSCLK based on the oscilloscope reading.
 //
-//    ** your answer here **
+//    ** MCO2 * MCO2PRE = 21.053 * 4 which is about 84 MHz. **
 //
 //    What is the peak to peak reading of the signal.
 //
-//    ** your answer here **
+//    ** 6.20 including the ringing, and without ringing 3.1 V **
 //
 //    Make a screen dump or photo of the oscilloscope output.
 //    Save the the picture as "bare_6_84mhz_high_speed"

openocd.gdb

@@ -16,7 +16,7 @@ monitor arm semihosting enable
 # send captured ITM to the file (fifo) /tmp/itm.log
 # (the microcontroller SWO pin must be connected to the programmer SWO pin)
 # 16000000 must match the core clock frequency
-monitor tpiu config internal /tmp/itm.log uart off 64000000 #16000000
+monitor tpiu config internal /tmp/itm.log uart off 16000000 # 64000000
 
 # OR: make the microcontroller SWO pin output compatible with UART (8N1)
 # 8000000 must match the core clock frequency