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Cargo.toml

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  • This project manages its dependencies using Cargo. Learn more
    stm32f4x.cfg 2.98 KiB
    # script for stm32f4x family
    
    #
    # stm32 devices support both JTAG and SWD transports.
    #
    source [find target/swj-dp.tcl]
    source [find mem_helper.tcl]
    
    if { [info exists CHIPNAME] } {
       set _CHIPNAME $CHIPNAME
    } else {
       set _CHIPNAME stm32f4x
    }
    
    set _ENDIAN little
    
    # Work-area is a space in RAM used for flash programming
    # By default use 32kB (Available RAM in smallest device STM32F410)
    if { [info exists WORKAREASIZE] } {
       set _WORKAREASIZE $WORKAREASIZE
    } else {
       set _WORKAREASIZE 0x8000
    }
    
    #jtag scan chain
    if { [info exists CPUTAPID] } {
       set _CPUTAPID $CPUTAPID
    } else {
       if { [using_jtag] } {
          # See STM Document RM0090
          # Section 38.6.3 - corresponds to Cortex-M4 r0p1
          set _CPUTAPID 0x4ba00477
       } {
          set _CPUTAPID 0x2ba01477
       }
    }
    
    swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
    dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
    
    if {[using_jtag]} {
       jtag newtap $_CHIPNAME bs -irlen 5
    }
    
    set _TARGETNAME $_CHIPNAME.cpu
    target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
    
    $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
    
    set _FLASHNAME $_CHIPNAME.flash
    flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
    
    # JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
    #
    # Since we may be running of an RC oscilator, we crank down the speed a
    # bit more to be on the safe side. Perhaps superstition, but if are
    # running off a crystal, we can run closer to the limit. Note
    # that there can be a pretty wide band where things are more or less stable.
    adapter_khz 2000
    
    adapter_nsrst_delay 100
    if {[using_jtag]} {
     jtag_ntrst_delay 100
    }
    
    reset_config srst_nogate
    
    if {![using_hla]} {
       # if srst is not fitted use SYSRESETREQ to
       # perform a soft reset
       cortex_m reset_config sysresetreq
    }
    
    $_TARGETNAME configure -event examine-end {
    	# Enable debug during low power modes (uses more power)
    	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
    	mmw 0xE0042004 0x00000007 0
    
    	# Stop watchdog counters during halt
    	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
    	mmw 0xE0042008 0x00001800 0
    }
    
    $_TARGETNAME configure -event trace-config {
    	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
    	# change this value accordingly to configure trace pins
    	# assignment
    	mmw 0xE0042004 0x00000020 0
    }
    
    $_TARGETNAME configure -event reset-init {
    	# # Configure PLL to boost clock to HSI x 4 (64 MHz)
    	# mww 0x40023804 0x08012008   ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
    	# mww 0x40023C00 0x00000102   ;# FLASH_ACR = PRFTBE | 2(Latency)
    	# mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
    	# sleep 10                    ;# Wait for PLL to lock
    	# mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
    	# mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
    
    	# Boost JTAG frequency
    	adapter_khz 8000
    }
    
    $_TARGETNAME configure -event reset-start {
    	# Reduce speed since CPU speed will slow down to 16MHz with the reset
    	adapter_khz 2000
    }