cleaning up

src/dma.rs

@@ -219,10 +219,7 @@ pub mod dma1 {
 
     fn start_transfer_s6_c4(ndtr: u16, par: u32, m0: u32) {
         let dma = unsafe { &*DMA1::ptr() };
-        asm::bkpt();
-        ipln!("ndtr {:04x}", ndtr);
-        ipln!("par  {:08x}", par);
-        ipln!("m0   {:08x}", m0);
+
         // nr data transfers
         dma.s6ndtr.write(|w| unsafe { w.ndt().bits(ndtr) });
         // peripheral address
@@ -271,7 +268,6 @@ pub mod dma1 {
         fn split(self, ahb1: &mut AHB1) -> Streams {
             //ahb.ahb1enr().modify(|_, w| w.dma1en().set_bit());
             // power and clk to dma1
-            ipln!("dma1en");
             ahb1.enr().modify(|_, w| w.dma1en().set_bit());
 
             // // reset the DMA control registers (stops all on-going transfers)
@@ -301,13 +297,8 @@ pub mod dma1 {
             // from or writing to a reserved address space". I think it's impossible
             // to get to that state with our type safe API and *safe* Rust.
             let dma = unsafe { &*DMA1::ptr() };
-            let mut nr = 0;
-            asm::bkpt();
 
-            while dma.hisr.read().tcif6().bit_is_clear() {
-                nr += 1;
-            }
-            asm::bkpt();
+            while dma.hisr.read().tcif6().bit_is_clear() {}
             dma.hifcr.write(|w| w.ctcif6().set_bit());
             dma.s6cr.modify(|_, w| w.en().clear_bit());