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Commit 702a3c9d authored by Per Lindgren's avatar Per Lindgren
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cleaning up

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with 13 additions and 283 deletions
src/dma.rs
+ 13
− 283
View file @ 702a3c9d
......@@ -67,6 +67,10 @@ pub trait DmaExt {
fn split(self, ahb: &mut AHB1) -> Self::Streams;
}
pub unsafe trait StartTransfer {
fn start_transfer(&mut self);
}
pub trait Dma {
// sXcr stream x configuration register
fn cr(&mut self) -> &dma2::S5CR;
......@@ -134,7 +138,8 @@ pub struct W;
pub struct Output<MODE> {
_mode: PhantomData<MODE>,
}
// === Usart1TxPin
//
pub unsafe trait Usart1TxStream<USART> {}
pub mod dma1 {
......@@ -198,6 +203,13 @@ pub mod dma1 {
}
}
unsafe impl<CHANNEL> super::StartTransfer for S0<CHANNEL> {
fn start_transfer(&mut self) {
// self.cr().write(..);
// self.cndtr().write(..);
}
}
// hifcr high interrupt flag clear register
// hisr high interrupt status register
// lifcr low interrupt flag clear register
......@@ -280,285 +292,3 @@ pub mod dma1 {
}
}
}
// impl Usart1TxStrAeam for S7<C4> {}
// impl Serial {
// pub fn write_all<S>(self, stream: S, buffer: B) where S: Usart1TxStream {}
// }
// macro_rules! dma {
// ($($DMAX:ident: ($dmaX:ident, $dmaXen:ident, $dmaXrst:ident, {
// $($CX:ident: (
// $ccrX:ident,
// $CCRX:ident,
// $cndtrX:ident,
// $CNDTRX:ident,
// $cparX:ident,
// $CPARX:ident,
// $cmarX:ident,
// $CMARX:ident,
// $htifX:ident,
// $tcifX:ident,
// $chtifX:ident,
// $ctcifX:ident,
// $cgifX:ident
// ),)+
// }),)+) => {
// $(
// pub mod $dmaX {
// use core::sync::atomic::{self, Ordering};
// use stm32f4x::{$DMAX, dma2};
// use dma::{CircBuffer, DmaExt, Error, Event, Half, Transfer};
// use rcc::AHB1;
// pub struct Channels((), $(pub $CX),+);
// $(
// pub struct $CX { _0: () }
// impl $CX {
// pub fn listen(&mut self, event: Event) {
// match event {
// Event::HalfTransfer => self.ccr().modify(|_, w| w.htie().set_bit()),
// Event::TransferComplete => {
// self.ccr().modify(|_, w| w.tcie().set_bit())
// }
// }
// }
// pub fn unlisten(&mut self, event: Event) {
// match event {
// Event::HalfTransfer => {
// self.ccr().modify(|_, w| w.htie().clear_bit())
// },
// Event::TransferComplete => {
// self.ccr().modify(|_, w| w.tcie().clear_bit())
// }
// }
// }
// // interrupt
// pub(crate) fn isr(&self) -> dma2::sr::R {
// // NOTE(unsafe) atomic read with no side effects
// unsafe { (*$DMAX::ptr()).sr.read() }
// }
// pub(crate) fn ifcr(&self) -> &dma2::IFCR {
// unsafe { &(*$DMAX::ptr()).cr }
// }
// pub(crate) fn ccr(&mut self) -> &dma2::$CCRX {
// unsafe { &(*$DMAX::ptr()).$ccrX }
// }
// pub(crate) fn cndtr(&mut self) -> &dma2::$CNDTRX {
// unsafe { &(*$DMAX::ptr()).$cndtrX }
// }
// pub(crate) fn cpar(&mut self) -> &dma2::$CPARX {
// unsafe { &(*$DMAX::ptr()).$cparX }
// }
// pub(crate) fn cmar(&mut self) -> &dma2::$CMARX {
// unsafe { &(*$DMAX::ptr()).$cmarX }
// }
// }
// impl<B> CircBuffer<B, $CX> {
// /// Peeks into the readable half of the buffer
// pub fn peek<R, F>(&mut self, f: F) -> Result<R, Error>
// where
// F: FnOnce(&B, Half) -> R,
// {
// let half_being_read = self.readable_half()?;
// let buf = match half_being_read {
// Half::First => &self.buffer[0],
// Half::Second => &self.buffer[1],
// };
// // XXX does this need a compiler barrier?
// let ret = f(buf, half_being_read);
// let isr = self.channel.isr();
// let first_half_is_done = isr.$htifX().bit_is_set();
// let second_half_is_done = isr.$tcifX().bit_is_set();
// if (half_being_read == Half::First && second_half_is_done) ||
// (half_being_read == Half::Second && first_half_is_done) {
// Err(Error::Overrun)
// } else {
// Ok(ret)
// }
// }
// /// Returns the `Half` of the buffer that can be read
// pub fn readable_half(&mut self) -> Result<Half, Error> {
// let isr = self.channel.isr();
// let first_half_is_done = isr.$htifX().bit_is_set();
// let second_half_is_done = isr.$tcifX().bit_is_set();
// if first_half_is_done && second_half_is_done {
// return Err(Error::Overrun);
// }
// let last_read_half = self.readable_half;
// Ok(match last_read_half {
// Half::First => {
// if second_half_is_done {
// self.channel.ifcr().write(|w| w.$ctcifX().set_bit());
// self.readable_half = Half::Second;
// Half::Second
// } else {
// last_read_half
// }
// }
// Half::Second => {
// if first_half_is_done {
// self.channel.ifcr().write(|w| w.$chtifX().set_bit());
// self.readable_half = Half::First;
// Half::First
// } else {
// last_read_half
// }
// }
// })
// }
// }
// impl<BUFFER, PAYLOAD, MODE> Transfer<MODE, BUFFER, $CX, PAYLOAD> {
// pub fn wait(mut self) -> (BUFFER, $CX, PAYLOAD) {
// // XXX should we check for transfer errors here?
// // The manual says "A DMA transfer error can be generated by reading
// // from or writing to a reserved address space". I think it's impossible
// // to get to that state with our type safe API and *safe* Rust.
// while self.channel.isr().$tcifX().bit_is_clear() {}
// self.channel.ifcr().write(|w| w.$cgifX().set_bit());
// self.channel.ccr().modify(|_, w| w.en().clear_bit());
// // TODO can we weaken this compiler barrier?
// // NOTE(compiler_fence) operations on `buffer` should not be reordered
// // before the previous statement, which marks the DMA transfer as done
// atomic::compiler_fence(Ordering::SeqCst);
// (self.buffer, self.channel, self.payload)
// }
// }
// )+
// }
// )+
// }
// }
// dma! {
// DMA1: (dma2, dma2en, dma2rst, {
// C1: (
// ccr1, CCR1,
// cndtr1, CNDTR1,
// cpar1, CPAR1,
// cmar1, CMAR1,
// htif1, tcif1,
// chtif1, ctcif1, cgif1
// ),
// C2: (
// ccr2, CCR2,
// cndtr2, CNDTR2,
// cpar2, CPAR2,
// cmar2, CMAR2,
// htif2, tcif2,
// chtif2, ctcif2, cgif2
// ),
// C3: (
// ccr3, CCR3,
// cndtr3, CNDTR3,
// cpar3, CPAR3,
// cmar3, CMAR3,
// htif3, tcif3,
// chtif3, ctcif3, cgif3
// ),
// C4: (
// ccr4, CCR4,
// cndtr4, CNDTR4,
// cpar4, CPAR4,
// cmar4, CMAR4,
// htif4, tcif4,
// chtif4, ctcif4, cgif4
// ),
// C5: (
// ccr5, CCR5,
// cndtr5, CNDTR5,
// cpar5, CPAR5,
// cmar5, CMAR5,
// htif5, tcif5,
// chtif5, ctcif5, cgif5
// ),
// C6: (
// ccr6, CCR6,
// cndtr6, CNDTR6,
// cpar6, CPAR6,
// cmar6, CMAR6,
// htif6, tcif6,
// chtif6, ctcif6, cgif6
// ),
// C7: (
// ccr7, CCR7,
// cndtr7, CNDTR7,
// cpar7, CPAR7,
// cmar7, CMAR7,
// htif7, tcif7,
// chtif7, ctcif7, cgif7
// ),
// }),
// DMA2: (dma2, dma2en, dma2rst, {
// C1: (
// ccr1, CCR1,
// cndtr1, CNDTR1,
// cpar1, CPAR1,
// cmar1, CMAR1,
// htif1, tcif1,
// chtif1, ctcif1, cgif1
// ),
// C2: (
// ccr2, CCR2,
// cndtr2, CNDTR2,
// cpar2, CPAR2,
// cmar2, CMAR2,
// htif2, tcif2,
// chtif2, ctcif2, cgif2
// ),
// C3: (
// ccr3, CCR3,
// cndtr3, CNDTR3,
// cpar3, CPAR3,
// cmar3, CMAR3,
// htif3, tcif3,
// chtif3, ctcif3, cgif3
// ),
// C4: (
// ccr4, CCR4,
// cndtr4, CNDTR4,
// cpar4, CPAR4,
// cmar4, CMAR4,
// htif4, tcif4,
// chtif4, ctcif4, cgif4
// ),
// C5: (
// ccr5, CCR5,
// cndtr5, CNDTR5,
// cpar5, CPAR5,
// cmar5, CMAR5,
// htif5, tcif5,
// chtif5, ctcif5, cgif5
// ),
// }),
// }
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