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Per Lindgren
stm32f4-hal
Commits
4bded63e
Commit
4bded63e
authored
7 years ago
by
Per Lindgren
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Stream trait works, but error on buffer
parent
5b1dfe92
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Changes
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2 changed files
src/dma.rs
+6
-6
6 additions, 6 deletions
src/dma.rs
src/serial.rs
+34
-38
34 additions, 38 deletions
src/serial.rs
with
40 additions
and
44 deletions
src/dma.rs
+
6
−
6
View file @
4bded63e
...
...
@@ -113,6 +113,8 @@ pub struct W;
pub
struct
Output
<
MODE
>
{
_mode
:
PhantomData
<
MODE
>
,
}
// === Usart1TxPin
pub
unsafe
trait
Usart1TxStream
<
USART
>
{}
pub
mod
dma1
{
use
core
::
marker
::
PhantomData
;
...
...
@@ -160,10 +162,7 @@ pub mod dma1 {
}
}
// === Usart1TxPin
pub
unsafe
trait
Usart1TxStream
<
USART
>
{}
unsafe
impl
Usart1TxStream
<
USART2
>
for
S5
<
C4
>
{}
unsafe
impl
super
::
Usart1TxStream
<
USART2
>
for
S5
<
C4
>
{}
pub
struct
Streams
(
pub
S4
<
C0
>
,
pub
S5
<
C0
>
);
...
...
@@ -183,7 +182,8 @@ pub mod dma1 {
// lifcr low interrupt flag clear register
// lisr low interrupt status register
impl
<
CHANNEL
>
S5
<
CHANNEL
>
{
// impl<CHANNEL> S5<CHANNEL> {
impl
S5
<
C4
>
{
// sXcr stream x configuration register
pub
(
crate
)
fn
cr
(
&
mut
self
)
->
&
dma2
::
S5CR
{
unsafe
{
&
(
*
DMA1
::
ptr
())
.s5cr
}
...
...
@@ -209,7 +209,7 @@ pub mod dma1 {
unsafe
{
&
(
*
DMA1
::
ptr
())
.s5ndtr
}
}
// s
0
par stream x peripheral address register
// s
X
par stream x peripheral address register
pub
(
crate
)
fn
par
(
&
mut
self
)
->
&
dma2
::
S5PAR
{
unsafe
{
&
(
*
DMA1
::
ptr
())
.s5par
}
}
...
...
This diff is collapsed.
Click to expand it.
src/serial.rs
+
34
−
38
View file @
4bded63e
...
...
@@ -8,11 +8,12 @@
use
core
::
sync
::
atomic
::{
self
,
Ordering
};
use
core
::
ptr
;
use
core
::
marker
::{
PhantomData
,
Unsize
};
use
cast
::
u16
;
use
hal
::
serial
;
use
nb
;
use
stm32f4x
::{
USART1
,
USART2
,
USART6
};
use
dma
::{
Static
,
Transfer
,
R
};
use
dma
::{
Static
,
Transfer
,
Usart1TxStream
,
R
};
// usart2
use
gpio
::
gpioa
::{
PA2
,
PA3
};
...
...
@@ -241,26 +242,21 @@ macro_rules! hal {
}
}
impl
Tx
<
$USARTX
>
{
pub
fn
write_all
<
A
,
B
,
C
>
(
pub
fn
write_all
<
A
,
B
,
S
>
(
self
,
mut
chan
:
C
,
mut
stream
:
S
,
buffer
:
B
,
)
->
Transfer
<
R
,
B
,
C
,
Self
>
)
->
Transfer
<
R
,
B
,
S
,
Self
>
where
A
:
Unsize
<
[
u8
]
>
,
B
:
Static
<
A
>
,
C
:
S
:
Usart1TxStream
<
$USARTX
>
{
// // write!(dma1, "hi {}", 1);
// let usart2 = self.0;
// if dma1.s6cr.read().en().bit_is_set() {
// return Err(dma::Error::InUse);
// }
// let buffer: &[u8] = buffer.lock();
// dma1.s6ndtr
// let buffer: &[u8] = buffer.borrow();
// stream.ndtr()
// .write(|w| unsafe { w.ndt().bits(u16(buffer.len()).unwrap()) });
// dma1.s6par
// .write(|w| unsafe { w.bits(&usart2.dr as *const _ as u32) });
...
...
@@ -284,7 +280,7 @@ macro_rules! hal {
// TODO can we weaken this compiler barrier?
// NOTE(compiler_fence) operations on `buffer` should not be reordered after
// the next statement, which starts the DMA transfer
atomic
::
compiler_fence
(
Ordering
::
SeqCst
);
//
atomic::compiler_fence(Ordering::SeqCst);
// chan.ccr().modify(|_, w| {
// w.mem2mem()
...
...
@@ -297,7 +293,7 @@ macro_rules! hal {
// .bit8()
// .minc()
// .set_bit()
// .pinc()
// .pinc()
chan
// .clear_bit()
// .circ()
// .clear_bit()
...
...
@@ -308,7 +304,7 @@ macro_rules! hal {
// });
Transfer
::
r
(
buffer
,
chan
,
self
)
Transfer
::
r
(
buffer
,
stream
,
self
)
}
}
...
...
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