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Commit 2bb50852 authored by Per Lindgren's avatar Per Lindgren
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first transition to singletons

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src/flash.rs
+ 1
− 1
View file @ 2bb50852
//! Flash memory
use stm32f30x::{flash, FLASH};
use stm32f4x::{flash, FLASH};
/// Extension trait to constrain the FLASH peripheral
pub trait FlashExt {
......
src/gpio.rs
+ 17
− 12
View file @ 2bb50852
......@@ -5,7 +5,7 @@
use core::marker::PhantomData;
use rcc::AHB;
use rcc::AHB1;
/// Extension trait to split a GPIO peripheral in independent pins and registers
pub trait GpioExt {
......@@ -13,7 +13,7 @@ pub trait GpioExt {
type Parts;
/// Splits the GPIO block into independent pins and registers
fn split(self, ahb: &mut AHB) -> Self::Parts;
fn split(self, ahb: &mut AHB1) -> Self::Parts;
}
/// Input mode (type state)
......@@ -95,9 +95,9 @@ macro_rules! gpio {
use core::marker::PhantomData;
use hal::digital::OutputPin;
use stm32f30x::{$gpioy, $GPIOX};
use stm32f4x::{$gpioy, $GPIOX};
use rcc::AHB;
use rcc::AHB1;
use super::{
AF4, AF5, AF6, AF7, Floating, GpioExt, Input, OpenDrain, Output,
PullDown, PullUp, PushPull,
......@@ -124,8 +124,9 @@ macro_rules! gpio {
impl GpioExt for $GPIOX {
type Parts = Parts;
fn split(self, ahb: &mut AHB) -> Parts {
ahb.enr().modify(|_, w| w.$iopxenr().enabled());
// GPIOA, GPIOB, GPIOC, GPIOD, GPIOAE, GPIOAH is on AHB1
fn split(self, ahb: &mut AHB1) -> Parts {
ahb.enr().modify(|_, w| w.$iopxenr().set_bit());
ahb.rstr().modify(|_, w| w.$iopxrst().set_bit());
ahb.rstr().modify(|_, w| w.$iopxrst().clear_bit());
......@@ -487,7 +488,7 @@ macro_rules! gpio {
}
}
gpio!(GPIOA, gpioa, gpioa, iopaen, ioparst, PAx, [
gpio!(GPIOA, gpioa, gpioa, gpioaen, gpioarst, PAx, [
PA0: (pa0, 0, Input<Floating>, AFRL),
PA1: (pa1, 1, Input<Floating>, AFRL),
PA2: (pa2, 2, Input<Floating>, AFRL),
......@@ -507,7 +508,7 @@ gpio!(GPIOA, gpioa, gpioa, iopaen, ioparst, PAx, [
// PA15: (15, Input<Floating>),
]);
gpio!(GPIOB, gpiob, gpiob, iopben, iopbrst, PBx, [
gpio!(GPIOB, gpiob, gpiob, gpioben, gpiobrst, PBx, [
PB0: (pb0, 0, Input<Floating>, AFRL),
PB1: (pb1, 1, Input<Floating>, AFRL),
PB2: (pb2, 2, Input<Floating>, AFRL),
......@@ -527,7 +528,8 @@ gpio!(GPIOB, gpiob, gpiob, iopben, iopbrst, PBx, [
PB15: (pb15, 15, Input<Floating>, AFRH),
]);
gpio!(GPIOC, gpioc, gpioc, iopcen, iopcrst, PCx, [
/*
gpio!(GPIOC, gpioc, gpiob, gpiocen, gpiocrst, PCx, [
PC0: (pc0, 0, Input<Floating>, AFRL),
PC1: (pc1, 1, Input<Floating>, AFRL),
PC2: (pc2, 2, Input<Floating>, AFRL),
......@@ -546,7 +548,7 @@ gpio!(GPIOC, gpioc, gpioc, iopcen, iopcrst, PCx, [
PC15: (pc15, 15, Input<Floating>, AFRH),
]);
gpio!(GPIOD, gpiod, gpioc, iopden, iopdrst, PDx, [
gpio!(GPIOD, gpiod, gpioc, gpioden, gpiodrst, PDx, [
PD0: (pd0, 0, Input<Floating>, AFRL),
PD1: (pd1, 1, Input<Floating>, AFRL),
PD2: (pd2, 2, Input<Floating>, AFRL),
......@@ -565,10 +567,10 @@ gpio!(GPIOD, gpiod, gpioc, iopden, iopdrst, PDx, [
PD15: (pd15, 15, Input<Floating>, AFRH),
]);
gpio!(GPIOE, gpioe, gpioc, iopeen, ioperst, PEx, [
gpio!(GPIOE, gpioe, gpioc, gpioeen, gpioerst, PEx, [
PE0: (pe0, 0, Input<Floating>, AFRL),
PE1: (pe1, 1, Input<Floating>, AFRL),
PE2: (pe2, 2, Input<Floating>, AFRL),
PE2: (pe2, 2, Input<Floating>, AFRL),gpio
PE3: (pe3, 3, Input<Floating>, AFRL),
PE4: (pe4, 4, Input<Floating>, AFRL),
PE5: (pe5, 5, Input<Floating>, AFRL),
......@@ -583,7 +585,9 @@ gpio!(GPIOE, gpioe, gpioc, iopeen, ioperst, PEx, [
PE14: (pe14, 14, Input<Floating>, AFRH),
PE15: (pe15, 15, Input<Floating>, AFRH),
]);
*/
/*
gpio!(GPIOF, gpiof, gpioc, iopfen, iopfrst, PFx, [
PF0: (pf0, 0, Input<Floating>, AFRL),
PF1: (pf1, 1, Input<Floating>, AFRL),
......@@ -593,3 +597,4 @@ gpio!(GPIOF, gpiof, gpioc, iopfen, iopfrst, PFx, [
PF9: (pf9, 9, Input<Floating>, AFRH),
PF10: (pf10, 10, Input<Floating>, AFRH),
]);
*/
src/lib.rs
+ 12
− 12
View file @ 2bb50852
//! HAL for the STM32F30x family of microcontrollers
//! HAL for the STM32F4x family of microcontrollers
//!
//! This is an implementation of the [`embedded-hal`] traits for the STM32F30x family of
//! This is an implementation of the [`embedded-hal`] traits for the STM32F4x family of
//! microcontrollers.
//!
//! [`embedded-hal`]: https://github.com/japaric/embedded-hal
......@@ -15,12 +15,10 @@
//!
//! # Examples
//!
//! Examples of *using* these abstractions can be found in the documentation of the [`f3`] crate.
//!
//! [`f3`]: https://docs.rs/f3/~0.5.1
//! See examples directory for generic usage
#![deny(missing_docs)]
#![deny(warnings)]
//#![deny(warnings)]
#![feature(never_type)]
#![no_std]
......@@ -28,15 +26,17 @@ extern crate cast;
extern crate cortex_m;
extern crate embedded_hal as hal;
extern crate nb;
pub extern crate stm32f413;
pub extern crate stm32f413 as stm32f4x;
// pub mod delay;
// pub mod flash;
// pub mod gpio;
pub mod flash;
pub mod gpio;
// pub mod i2c;
// pub mod prelude;
// pub mod rcc;
pub mod prelude;
pub mod rcc;
// pub mod serial;
// pub mod spi;
// pub mod time;
pub mod time;
// pub mod timer;
pub mod led;
src/prelude.rs
+ 2
− 2
View file @ 2bb50852
......@@ -2,6 +2,6 @@
pub use gpio::GpioExt as _stm32f30x_hal_gpio_GpioExt;
pub use hal::prelude::*;
pub use rcc::RccExt as _stm32f30x_hal_rcc_RccExt;
pub use time::U32Ext as _stm32f30x_hal_time_U32Ext;
pub use rcc::RccExt as _stm32f4x_hal_rcc_RccExt;
// pub use time::U32Ext as _stm32f30x_hal_time_U32Ext;
pub use flash::FlashExt as _stm32f30x_hal_flash_FlashExt;
src/rcc.rs
+ 15
− 15
View file @ 2bb50852
......@@ -3,7 +3,7 @@
use core::cmp;
use cast::u32;
use stm32f30x::{rcc, RCC};
use stm32f4x::{rcc, RCC};
use flash::ACR;
use time::Hertz;
......@@ -17,7 +17,7 @@ pub trait RccExt {
impl RccExt for RCC {
fn constrain(self) -> Rcc {
Rcc {
ahb: AHB { _0: () },
ahb1: AHB1 { _0: () },
apb1: APB1 { _0: () },
apb2: APB2 { _0: () },
cfgr: CFGR {
......@@ -33,7 +33,7 @@ impl RccExt for RCC {
/// Constrained RCC peripheral
pub struct Rcc {
/// AMBA High-performance Bus (AHB) registers
pub ahb: AHB,
pub ahb1: AHB1,
/// Advanced Peripheral Bus 1 (APB1) registers
pub apb1: APB1,
/// Advanced Peripheral Bus 2 (APB2) registers
......@@ -42,20 +42,20 @@ pub struct Rcc {
pub cfgr: CFGR,
}
/// AMBA High-performance Bus (AHB) registers
pub struct AHB {
/// AMBA High-performance Bus (AHB1) registers
pub struct AHB1 {
_0: (),
}
impl AHB {
pub(crate) fn enr(&mut self) -> &rcc::AHBENR {
impl AHB1 {
pub(crate) fn enr(&mut self) -> &rcc::AHB1ENR {
// NOTE(unsafe) this proxy grants exclusive access to this register
unsafe { &(*RCC::ptr()).ahbenr }
unsafe { &(*RCC::ptr()).ahb1enr }
}
pub(crate) fn rstr(&mut self) -> &rcc::AHBRSTR {
pub(crate) fn rstr(&mut self) -> &rcc::AHB1RSTR {
// NOTE(unsafe) this proxy grants exclusive access to this register
unsafe { &(*RCC::ptr()).ahbrstr }
unsafe { &(*RCC::ptr()).ahb1rstr }
}
}
......@@ -222,7 +222,7 @@ impl CFGR {
if let Some(pllmul_bits) = pllmul_bits {
// use PLL as source
rcc.cfgr.write(|w| unsafe { w.pllmul().bits(pllmul_bits) });
// rcc.cfgr.write(|w| unsafe { w.pllmul().bits(pllmul_bits) });
rcc.cr.write(|w| w.pllon().set_bit());
......@@ -236,8 +236,8 @@ impl CFGR {
.bits(ppre1_bits)
.hpre()
.bits(hpre_bits)
.sw()
.bits(0b10)
// .sw()
// .bits(0b10)
});
} else {
// use HSI as source
......@@ -250,8 +250,8 @@ impl CFGR {
.bits(ppre1_bits)
.hpre()
.bits(hpre_bits)
.sw()
.bits(0b00)
// .sw()
// .bits(0b00)
});
}
......
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