gpio.rs

//! Simple access to gpio
#![deny(unsafe_code)]
#![feature(proc_macro)]
#![no_std]

extern crate cortex_m;
extern crate cortex_m_rtfm as rtfm;
extern crate stm32f40x;

use rtfm::app;

app! {
    device: stm32f40x,
}

fn wait(i: u32) {
    for _ in 0..i {
        cortex_m::asm::nop(); // no operation (cannot be optimized out)
    }
}

// see the Reference Manual RM0368 (www.st.com/resource/en/reference_manual/dm00096844.pdf)
// rcc,     chapter 6
// gpio,    chapter 8

fn init(p: init::Peripherals) {
    // power on GPIOA, RM0368 6.3.11
    p.RCC.ahb1enr.modify(|_, w| w.gpioaen().set_bit());

    // configure PA5 as output, RM0368 8.4.1
    p.GPIOA.moder.modify(|_, w| w.moder5().bits(1));

    // loop {
    //     // set PA5 high, RM0368 8.4.6
    //     p.GPIOA.odr.modify(|_, w| w.odr5().bit(true));
    //     wait(10_000);

    //     // set PA5 low, RM0368 8.4.6
    //     p.GPIOA.odr.modify(|_, w| w.odr5().bit(false));
    //     wait(10_000);
    // }

    // rewrite the above code to have the GPIO as output
    // and alter the data output through the BSRR register
    // this is more efficient as the read register (in modify)
    // is not needed.

    loop {
        // set PA5 high, RM0368 8.4.7
        p.GPIOA.bsrr.write(|w| w.bs5().set_bit());
        wait(10_000);

        // set PA5 low, RM0368 8.4.7
        p.GPIOA.bsrr.write(|w| w.br5().set_bit());
        wait(10_000);
    }
}

#[inline(never)]
fn idle() -> ! {
    loop {
        rtfm::wfi();
    }
}