sleep with wakeup from true sleep mode

examples/sleep.rs

@@ -81,6 +81,9 @@ fn main() -> ! {
     p.NVIC.enable(Interrupt::EXTI1);
     // enable gpioa (input mode on reset)
     r.RCC.ahb1enr.modify(|_, w| w.gpioaen().set_bit());
+    r.GPIOA.pupdr.modify(|_, w| w.pupdr1().pull_up());
+
+    // SYSCFG.exti1 is PAx (0000) by reset
     // enbable masking of EXTI line 1
     r.EXTI.imr.modify(|_, w| w.mr1().set_bit());
     // trigger on falling edge
@@ -91,9 +94,12 @@ fn main() -> ! {
 
     // p.NVIC.set_pending(Interrupt::EXTI1);
 
-    dbg_disable();
-    asm::wfi();
-    dbg_enable();
+    loop {
+        dbg_disable();
+        asm::wfi();
+        dbg_enable();
+        asm::bkpt();
+    }
     // asm::bkpt();
     loop {}
 }
@@ -122,7 +128,7 @@ use cortex_m::interrupt::Nr;
 fn exti1() {
     // dbg_enable();
     // asm::bkpt();
-    blink2();
+    blink2(); // it will take some time so bounces are likely gone
 
     // // let's try to "fake" access to GPIOA
     // // let g = stm32f40x::GPIOA {
@@ -132,13 +138,7 @@ fn exti1() {
 
     // clear pending state
     let exti = unsafe { &*stm32f40x::EXTI::ptr() };
-    exti.imr.modify(|_, w| w.mr1().clear_bit());
-    exti.pr.reset();
-
-    let nvic = unsafe { &*cortex_m::peripheral::NVIC::ptr() };
-    let nr = Interrupt::EXTI1.nr();
-    unsafe { nvic.icpr[usize::from(nr / 32)].write(1 << (nr % 32)) };
-    unsafe { nvic.icer[usize::from(nr / 32)].write(1 << (nr % 32)) };
+    exti.pr.write(|w| w.pr1().set_bit());
 }
 
 // define the hard fault handler