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timer.rs 4.35 KiB
//! Timer
use core::any::{Any, TypeId};
use cast::{u16, u32};
use hal;
use nb::{self, Error};
use stm32f40x::{TIM1, TIM2, TIM3, TIM4, TIM5, TIM9, TIM10, TIM11, RCC};
/// Channel associated to a timer
#[derive(Clone, Copy, Debug)]
pub enum Channel {
/// TxC1
_1,
/// TxC2
_2,
/// TxC3
_3,
/// TxC4
_4,
}
/// `hal::Timer` implementation
pub struct Timer<'a, T>(pub &'a T)
where
T: 'a;
impl<'a, T> Clone for Timer<'a, T> {
fn clone(&self) -> Self {
*self
}
}
impl<'a, T> Copy for Timer<'a, T> {}
macro_rules! impl_Timer {
($TIM:ident, $APB:ident) => {
impl<'a> Timer<'a, $TIM>
{
/// Initializes the timer with a periodic timeout of `frequency` Hz
///
/// NOTE After initialization, the timer will be in the paused state.
pub fn init<P>(&self, period: P, rcc: &RCC)
where
P: Into<::$APB::Ticks>,
{
self.init_(period.into(), rcc)
}
fn init_(&self, timeout: ::$APB::Ticks, rcc: &RCC) {
let tim = self.0;
// Enable TIMx
if tim.get_type_id() == TypeId::of::<TIM1>() {
rcc.apb2enr.modify(|_, w| w.tim1en().set_bit());
} else if tim.get_type_id() == TypeId::of::<TIM2>() {
rcc.apb1enr.modify(|_, w| w.tim2en().set_bit());
} else if tim.get_type_id() == TypeId::of::<TIM3>() {
rcc.apb1enr.modify(|_, w| w.tim3en().set_bit());
} else if tim.get_type_id() == TypeId::of::<TIM4>() {
rcc.apb1enr.modify(|_, w| w.tim4en().set_bit());
} else if tim.get_type_id() == TypeId::of::<TIM5>() {
rcc.apb1enr.modify(|_, w| w.tim5en().set_bit());
} else if tim.get_type_id() == TypeId::of::<TIM9>() {
rcc.apb2enr.modify(|_, w| w.tim9en().set_bit());
} else if tim.get_type_id() == TypeId::of::<TIM10>() {
rcc.apb2enr.modify(|_, w| w.tim10en().set_bit());
} else if tim.get_type_id() == TypeId::of::<TIM11>() {
rcc.apb2enr.modify(|_, w| w.tim11en().set_bit());