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Per Lindgren
cortex-m-fork
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itm
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itm
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20
v0.4.2
v0.4.1
v0.4.0
v0.1.7
v0.2.12
v0.3.1
v0.3.0
v0.2.11
v0.2.10
v0.2.9
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v0.2.7
v0.2.6
v0.2.5
v0.2.4
v0.2.3
v0.2.2
v0.2.1
v0.2.0
v0.1.6
22 results
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Created with Raphaël 2.2.0
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Sep
itm packaging according to CMSIS
itm
itm
Auto merge of #80 - japaric:send, r=japaric
v0.4.2 master
v0.4.2 master
impl Send for all the peripherals
v0.4.1
v0.4.1
v0.4.1
Merge pull request #78 from japaric/reexport
reexport Peripherals at the root for convenience
update changelog
v0.4.0
v0.4.0
Auto merge of #77 - japaric:v4, r=japaric
v0.4.0
Auto merge of #76 - japaric:thumbv6m, r=japaric
fixes and make sure the whole documentation is visible on docs.rs
hide ARMv7-M only peripherals on thumbv6m-none-eabi
Auto merge of #75 - japaric:syst, r=japaric
better document the SYST API
Auto merge of #70 - japaric:safe-static-mut, r=japaric
address review comments
Auto merge of #69 - japaric:revise-api, r=japaric
fix thumbv6m build
address review comments
Auto merge of #72 - japaric:cm7-r0p1, r=japaric
cache the Xargo directory
Auto merge of #73 - japaric:itm, r=japaric
make `Stim::write_*` methods take `&mut self` instead of `&self`
add a Cargo feature, cm7-r0p1, to fix a Cortex-M7 BASEPRI erratum
revise peripheral API
Auto merge of #71 - japaric:unimplemented-asm, r=japaric
inline(always) -> inline
map asm! ops to unimplemented! on non ARM targets
safe `&'static mut` references through a runtime checked macro
document `set_fpu_access_mode` footgun
Auto merge of #62 - hannobraun:update-nvic, r=japaric
Fix `IPR` representation on ARMv6-M
Make all available NVIC registers accessible
Auto merge of #66 - japaric:unhide-steal, r=japaric
docs: unhide `Peripherals::steal` method
Auto merge of #65 - japaric:singletons, r=japaric
fix travis
fix tests
s/all/take/g s/_all/steal/g
turn peripherals into scoped singletons
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