openocd.gdb comment fixed and ext itm launch config added

.vscode/launch.json

@@ -62,6 +62,7 @@
                 "target/stm32f4x.cfg"
             ],
             "postLaunchCommands": [
+                // sets a breakpoint at the HardFault (won't show in `vscode`, but `gdb` will break)
                 "b HardFault"
             ],
             "cwd": "${workspaceRoot}"
@@ -96,6 +97,33 @@
             },
             "cwd": "${workspaceRoot}"
         },
+        // launch configuration for using an external itm viewer
+        // $ tail -f /tmp/itm.log
+        // or, prior to launching the bebug session
+        // $ mkfifo /tmp/itm.log
+        // $ itmdump -f /tmp/itm.log -F
+        {
+            "type": "cortex-debug",
+            "request": "launch",
+            "servertype": "openocd",
+            "name": "itm 16Mhz /tmp/itm.log (debug)",
+            "preLaunchTask": "cargo build --example itm",
+            "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm",
+            // uses local config files
+            "configFiles": [
+                "./stlink.cfg",
+                "./stm32f4x.cfg"
+            ],
+            "postLaunchCommands": [
+                // sets the core clock to 16000000 (see ./stm32f4x.cfg)
+                "monitor reset init",
+                // 16000000 must match the core clock frequency
+                "monitor tpiu config internal /tmp/itm.log uart off 16000000",
+                // enable ITM port 0
+                "monitor itm port 0 on"
+            ],
+            "cwd": "${workspaceRoot}"
+        },
         {
             "type": "cortex-debug",
             "request": "launch",

openocd.gdb

@@ -23,7 +23,7 @@ monitor tpiu config internal /tmp/itm.log uart off 16000000
 # 2000000 is the frequency of the SWO pin
 # monitor tpiu config external uart off 8000000 2000000
 
-# # enable ITM port 0
+# enable ITM port 0
 monitor itm port 0 on
 
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