bare6_nightly.rs

//! bare6.rs
//!
//! Clocking
//!
//! What it covers:
//! - using svd2rust generated API
//! - setting the clock via script (again)
//! - routing the clock to a PIN for monitoring by an oscilloscope
//! - changing the clock using Rust code
//!

#![no_main]
#![no_std]
#![feature(uniform_paths)]
#![feature(type_alias_enum_variants)]

extern crate panic_halt;

use cortex_m::{iprintln, peripheral::itm::Stim};
use cortex_m_rt::entry;

use stm32f4::stm32f413;
use stm32f413::{DWT, GPIOA, GPIOC, RCC};

#[entry]
fn main() -> ! {
    let p = stm32f413::Peripherals::take().unwrap();
    let mut c = stm32f413::CorePeripherals::take().unwrap();

    let stim = &mut c.ITM.stim[0];
    iprintln!(stim, "Hello, bare6!");

    c.DWT.enable_cycle_counter();
    unsafe {
        c.DWT.cyccnt.write(0);
    }
    let t = DWT::get_cycle_count();
    iprintln!(stim, "{}", t);

    clock_out(&p.RCC, &p.GPIOC);
    // clock::set_84_mhz(rcc, flash);
    idle(stim, p.RCC, p.GPIOA);

    loop {}
}

// // user application
fn idle(stim: &mut Stim, rcc: RCC, gpioa: GPIOA) {
    iprintln!(stim, "idle");

    // power on GPIOA, RM0368 6.3.11
    rcc.ahb1enr.modify(|_, w| w.gpioaen().set_bit());

    // configure PA5 as output, RM0368 8.4.1
    gpioa.moder.modify(|_, w| w.moder5().bits(1));

    // at 16 Mhz, 8_000_000 cycles = period 0.5s
    // at 64 Mhz, 4*8_000_000 cycles = period 0.5s
    // let cycles = 8_000_000;
    let cycles = 4 * 8_000_000;

    loop {
        iprintln!(stim, "on {}", DWT::get_cycle_count());
        // set PA5 high, RM0368 8.4.7
        gpioa.bsrr.write(|w| w.bs5().set_bit());
        wait_cycles(cycles);

        iprintln!(stim, "off {}", DWT::get_cycle_count());
        // set PA5 low, RM0368 8.4.7
        gpioa.bsrr.write(|w| w.br5().set_bit());