timing_task, all questions done

.cargo/config

@@ -5,10 +5,10 @@
 [target.'cfg(all(target_arch = "arm", target_os = "none"))']
 # uncomment ONE of these three option to make `cargo run` start a GDB session
 # which option to pick depends on your system
-# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+runner = "arm-none-eabi-gdb -q -x openocd.gdb"
 # runner = "gdb-multiarch -q -x openocd.gdb"
 # runner = "gdb -q -x openocd.gdb"
-runner = "probe-run --chip STM32F411RETx"
+# runner = "probe-run --chip STM32F411RETx"
 
 rustflags = [
   # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x

examples/timing_task.rs

@@ -82,10 +82,23 @@ const APP: () = {
 // (gdb) x 0xe0001004
 //
 // [Your answer here]
+/*
+(gdb) x/d 0xe0001004
+0xe0001004:     11
+*/
 //
 // (gdb) disassemble
 //
 // [Your answer here]
+/*
+(gdb) disassemble 
+Dump of assembler code for function timing_task::APP::EXTI0:
+=> 0x08000232 <+0>:     bkpt    0x0000
+   0x08000234 <+2>:     movs    r0, #0
+   0x08000236 <+4>:     msr     BASEPRI, r0
+   0x0800023a <+8>:     bx      lr
+End of assembler dump.
+*/
 //
 // You should see that we hit the breakpoint in `exti0`, and
 // that the code complies to the objdump EXTI disassembly.
@@ -96,10 +109,16 @@ const APP: () = {
 // What was the software latency observed to enter the task?
 //
 // [Your answer here]
+/*
+None, only hardware latenvy to enter the task.
+*/
 //
 // Does RTIC infer any overhead for launching the task?
 //
 // [Your answer here]
+/*
+No, the MCU jumps strait to the first useful intstruction in the exception.
+*/
 //
 // Now we can continue to measure the round trip time.
 //
@@ -110,6 +129,10 @@ const APP: () = {
 // (gdb) x 0xe0001004
 //
 // [Your answer here]
+/*
+(gdb) x/d 0xe0001004
+0xe0001004:     23
+*/
 //
 // Looking at the EXTI0 (exti0) code, we see two additional
 // instructions used to restore the BASEPRI register.