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output1.txt
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<?xml version="1.0" encoding="utf-8" standalone="no"?>
<device schemaVersion="1.1"
xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<name>STM32F411</name>
<version>1.1</version>
<description>STM32F411</description>
<!-- details about the cpu embedded in the device -->
<cpu>
<name>CM4</name>
<revision>r1p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>false</fpuPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<!--Bus Interface Properties-->
<!--Cortex-M4 is byte addressable-->
<addressUnitBits>8</addressUnitBits>
<!--the maximum data bit width accessible within a single transfer-->
<width>32</width>
<!--Register Default Properties-->
<size>0x20</size>
<resetValue>0x0</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>ADC_Common</name>
<description>ADC common registers</description>
<groupName>ADC</groupName>
<baseAddress>0x40012300</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x9</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>FPU</name>
<description>FPU interrupt</description>
<value>81</value>
</interrupt>
<registers>
<register>
<name>CSR</name>
<displayName>CSR</displayName>
<description>ADC Common status register</description>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OVR3</name>
<description>Overrun flag of ADC3</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STRT3</name>
<description>Regular channel Start flag of ADC
3</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>JSTRT3</name>
<description>Injected channel Start flag of ADC
3</description>
<bitOffset>19</bitOffset>