Eh, got nowhere. Strange readings.

examples/bare4.rs

@@ -8,6 +8,9 @@
 extern crate cortex_m;
 extern crate cortex_m_rt;
 
+#[macro_use]
+extern crate cortex_m_debug;
+
 // Peripheral addresses as constants
 #[rustfmt_skip]
 mod address {
@@ -45,12 +48,22 @@ fn wait(i: u32) {
 }
 
 fn main() {
+    ipln!("Program init!");
+    sprintln!("yow fam");
     // power on GPIOA
+    // RRC_AHB1ENR == RCC AHB1 clock enable register, offset 0x30
     let r = read_u32(RCC_AHB1ENR); // read
+    // OR:ing with 1 means putting bit 0 to 1. This enables IO port A clock Enable!!!!
     write_u32(RCC_AHB1ENR, r | 1); // set enable
 
     // configure PA5 as output
+    // General Purpose Input Output
+    // Reading, Bit-wise AND, !(0b11 << (10)), putting this value in r
+    // r takes on the value as the same register values, EXCEPT 00 in place of the 5*2 spot.
     let r = read_u32(GPIOA_MODER) & !(0b11 << (5 * 2)); // read and mask
+
+    // Write to MODER (mode register) , 
+    // 00 | 0b01 shifted 10, thus, MODER5 = 01, General Purpose Output Mode!
     write_u32(GPIOA_MODER, r | 0b01 << (5 * 2)); // set output mode
 
     // and alter the data output through the BSRR register
@@ -58,11 +71,28 @@ fn main() {
 
     loop {
         // set PA5 high
+        // BSRR = Bit Set/Reset Register
+        // Sets bit 5 to 1
         write_u32(GPIOA_BSRR, 1 << 5); // set bit, output hight (turn on led)
         wait(10_000);
         
+        let uw = read_u32(GPIOA_BSRR);
+        sprintln!("uw {:#b}", uw);
+        cortex_m::asm::bkpt();
+        
+        // Attempt at read and mask
+        let y: u16 = (0b1 << 5);
+        sprintln!("y: {:#b}", y);
+        let z: u32 = (!y) as u32;
+        sprintln!("z: {:#b}", z);
+        let x: u32 = (read_u32(GPIOA_BSRR));
+        sprintln!("x: {:#b}", x);
+        write_u32(GPIOA_BSRR, x | (0b1 << 5)); // clear bit, output low (turn off led)
+        
+        cortex_m::asm::bkpt();
         // set PA5 low
-        write_u32(GPIOA_BSRR, 1 << (5 + 16)); // clear bit, output low (turn off led)
+        // Adding a HALF-WORD (16 bits) resets the corresponding Bit!!!!
+        //write_u32(GPIOA_BSRR, 1 << (5 + 16)); // clear bit, output low (turn off led)
         wait(10_000);
     }
 }
@@ -79,6 +109,10 @@ fn main() {
 // document each low level access *code* by the appropriate section in the
 // data sheet
 // 
+// >>> You can find all the BASE boundary addresses @ 2.3, where we can see the AHB1/AHB2 Buses
+//      and their belonging peripherals + their memory addresses.
+//      From that point then, we'll find the offsets within each of the peripherals.
+//
 // >>> 6.3.11:
 //      RCC APB1 peripheral clock enable registe
 //      Address Offset: 0x40