Commit 9154ed49 authored by DevDoggo's avatar DevDoggo

Finished Part 4a

parents
[target.thumbv6m-none-eabi]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=lld",
"-Z", "linker-flavor=ld.lld",
# "-C", "linker=arm-none-eabi-ld",
# "-Z", "linker-flavor=ld",
]
[target.thumbv7m-none-eabi]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=lld",
"-Z", "linker-flavor=ld.lld",
# "-C", "linker=arm-none-eabi-ld",
# "-Z", "linker-flavor=ld",
]
[target.thumbv7em-none-eabi]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
"-C", "linker=lld",
"-Z", "linker-flavor=ld.lld",
# "-C", "linker=arm-none-eabi-ld",
# "-Z", "linker-flavor=ld",
]
[target.thumbv7em-none-eabihf]
runner = 'arm-none-eabi-gdb'
rustflags = [
"-C", "link-arg=-Tlink.x",
#"-C", "linker=lld",
#"-Z", "linker-flavor=ld.lld",
"-C", "linker=arm-none-eabi-ld",
"-Z", "linker-flavor=ld",
]
target remote :3333
# print demangled symbols by default
set print asm-demangle on
monitor arm semihosting enable
# # send captured ITM to the file itm.fifo
# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
# # 8000000 must match the core clock frequency
# monitor tpiu config internal itm.fifo uart off 8000000
# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
# # 2000000 is the frequency of the SWO pin
# monitor tpiu config external uart off 8000000 2000000
# # enable ITM port 0
# monitor itm port 0 on
load
step
**/*.rs.bk
.gdb_history
Cargo.lock
target/
language: rust
matrix:
include:
- env: TARGET=thumbv6m-none-eabi
rust: nightly
addons:
apt:
sources:
- debian-sid
packages:
- binutils-arm-none-eabi
- env: TARGET=thumbv7m-none-eabi
rust: nightly
addons:
apt:
sources:
- debian-sid
packages:
- binutils-arm-none-eabi
- env: TARGET=thumbv7em-none-eabi
rust: nightly
addons:
apt:
sources:
- debian-sid
packages:
- binutils-arm-none-eabi
- env: TARGET=thumbv7em-none-eabihf
rust: nightly
addons:
apt:
sources:
- debian-sid
packages:
- binutils-arm-none-eabi
before_install: set -e
install:
- bash ci/install.sh
script:
- bash ci/script.sh
after_script: set +e
cache: cargo
before_cache:
# Travis can't cache files that are not readable by "others"
- chmod -R a+r $HOME/.cargo
branches:
only:
- staging
- trying
notifications:
email:
on_success: never
# Change Log
All notable changes to this project will be documented in this file.
This project adheres to [Semantic Versioning](http://semver.org/).
## [Unreleased]
## [v0.2.7] - 2018-04-24
### Changed
- Bumped the dependency of `cortex-m-rt` to v0.4.0.
## [v0.2.6] - 2018-04-09
### Changed
- The documentation to instruct the user to use Cargo instead of Xargo
## [v0.2.5] - 2018-02-26
### Added
- Comments to Cargo.toml and Xargo.toml to make it easier to try the examples.
### Fixed
- The `allocator` example to use the `#[global_allocator]` feature.
## [v0.2.4] - 2018-01-26
### Changed
- Disable ThinLTO which causes extreme binary size bloat. See rust-lang/rust#47770 for details.
## [v0.2.3] - 2018-01-20
### Changed
- Tweaked docs. Instruction steps are now numbered.
### Removed
- The `CARGO_INCREMENTAL=1` workaround has been removed since it's now controlled via Cargo.toml and
we have the setting disabled in the template.
## [v0.2.2] - 2018-01-17
### Added
- Troubleshooting documentation: how to workaround the "Ignoring packet error, continuing..." GDB
error.
### Changed
- Disabled incremental compilation and parallel codegen on the dev profile to reduce the changes of
running into rust-lang/rust#47074.
- Bumped the version of the `cortex-m-rt` dependency to v0.3.12.
## [v0.2.1] - 2017-07-14
### Added
- Troubleshooting documentation: how to fix the error of overwriting the
`.cargo/config` file when you meant to append text to it.
### Changed
- Xargo.toml: Changed the source of the `compiler-builtins` crate from git to
the `rust-src` component.
- Expanded the `device` example to do some I/O.
## [v0.2.0] - 2017-07-07
### Changed
- [breaking-change] Bumped the cortex-m and cortex-m-rt versions to v0.3.0.
## [v0.1.8] - 2017-05-30
### Changed
- Bumped the cortex-m-rt dependency to v0.2.3, and documented the `_stext`
symbol (see memory.x).
## [v0.1.7] - 2017-05-27
### Added
- Documentation and an example about how to use the heap and a dynamic memory
allocator.
### Changed
- Bumped the `cortex-m-rt` dependency to v0.2.2
- Bumped the `cortex-m` dependency to v0.2.7
## [v0.1.6] - 2017-05-26
### Added
- Set the default runner in .cargo/config to `arm-none-eabi-gdb`. Now `xargo
run` will build the program and start a debug session.
## [v0.1.5] - 2017-05-16
### Added
- A warning about using CARGO_INCREMENTAL to the how to use and the
troubleshooting sections.
## [v0.1.4] - 2017-05-13
### Added
- A dependencies section to the documentation
### Changed
- Extend troubleshooting section
## [v0.1.3] - 2017-05-13
### Added
- A troubleshooting section to the documentation
### Changed
- Bumped the cortex-m crate version to v0.2.6
## [v0.1.2] - 2017-05-07
### Fixed
- .gdbinit: jump to reset handler after loading the program.
## [v0.1.1] - 2017-04-27
### Changed
- Bumped the version of the `cortex-m-rt` dependency to v0.2.0. NOTE that the
instantiation steps have slightly changed, the `memory.x` file changed,
because of this.
## v0.1.0 - 2017-04-25
- Initial release
[Unreleased]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.7...HEAD
[v0.2.7]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.6...v0.2.7
[v0.2.6]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.5...v0.2.6
[v0.2.5]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.4...v0.2.5
[v0.2.4]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.3...v0.2.4
[v0.2.3]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.2...v0.2.3
[v0.2.2]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.1...v0.2.2
[v0.2.1]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.0...v0.2.1
[v0.2.0]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.8...v0.2.0
[v0.1.8]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.7...v0.1.8
[v0.1.7]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.6...v0.1.7
[v0.1.6]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.5...v0.1.6
[v0.1.5]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.4...v0.1.5
[v0.1.4]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.3...v0.1.4
[v0.1.3]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.2...v0.1.3
[v0.1.2]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.1...v0.1.2
[v0.1.1]: https://github.com/japaric/cortex-m-quickstart/compare/v0.1.0...v0.1.1
[package]
authors = ["Fredrik <frepet-5@student.ltu.se>"]
# categories = ["embedded", "no-std"]
# description = "A template for building applications for ARM Cortex-M microcontrollers"
# keywords = ["arm", "cortex-m", "template"]
# license = "MIT OR Apache-2.0"
name = "app_a4"
version = "0.2.7"
[dependencies]
cortex-m = "0.4.0"
cortex-m-semihosting = "0.2.0"
panic-abort = "0.1.1"
panic-semihosting = "0.1.0"
# Uncomment for the allocator example.
# alloc-cortex-m = "0.3.3"
[dependencies.stm32f103xx]
# features = ["rt"] # this feature indicates that the device crate will provide the vector table
# version = "0.7.5"
# Uncomment for the device example.
[dependencies.stm32f40x]
features = ["rt"] # see comment above
git = "https://gitlab.henriktjader.com/pln/STM32F40x"
[dependencies.cortex-m-rt]
version = "0.3.15"
features = ["abort-on-panic"]
[profile.release]
debug = true
lto = true
# opt-level = "s"
This diff is collapsed.
Copyright (c) 2018
Permission is hereby granted, free of charge, to any
person obtaining a copy of this software and associated
documentation files (the "Software"), to deal in the
Software without restriction, including without
limitation the rights to use, copy, modify, merge,
publish, distribute, sublicense, and/or sell copies of
the Software, and to permit persons to whom the Software
is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice
shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
# `cortex-m-quickstart`
> A template for building applications for ARM Cortex-M microcontrollers
# [Documentation](https://docs.rs/cortex-m-quickstart)
# License
Licensed under either of
- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
http://www.apache.org/licenses/LICENSE-2.0)
- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
at your option.
## Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
dual licensed as above, without any additional terms or conditions.
status = [
"continuous-integration/travis-ci/push",
]
\ No newline at end of file
use std::env;
use std::fs::File;
use std::io::Write;
use std::path::PathBuf;
fn main() {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
File::create(out.join("memory.x"))
.unwrap()
.write_all(include_bytes!("memory.x"))
.unwrap();
println!("cargo:rustc-link-search={}", out.display());
println!("cargo:rerun-if-changed=build.rs");
println!("cargo:rerun-if-changed=memory.x");
}
set -euxo pipefail
main() {
rustup target add $TARGET
}
main
set -euxo pipefail
main() {
local td=$(mktemp -d)
git clone . $td
pushd $td
cat >memory.x <<'EOF'
MEMORY
{
/* NOTE K = KiBi = 1024 bytes */
FLASH : ORIGIN = 0x08000000, LENGTH = 256K
RAM : ORIGIN = 0x20000000, LENGTH = 40K
}
EOF
local examples=(
crash
hello
override-exception-handler
panic
)
for ex in "${examples[@]}"; do
cargo build --target $TARGET --example $ex
cargo build --target $TARGET --example $ex --release
done
# ITM is not available on Cortex-M0
if [ $TARGET != thumbv6m-none-eabi ]; then
local ex=itm
cargo build --target $TARGET --example $ex
cargo build --target $TARGET --example $ex --release
examples+=( $ex )
fi
# Allocator example needs an extra dependency
cat >>Cargo.toml <<'EOF'
[dependencies.alloc-cortex-m]
version = "0.3.3"
EOF
local ex=allocator
cargo build --target $TARGET --example $ex
cargo build --target $TARGET --example $ex --release
examples+=( $ex )
# Device example needs an extra dependency
if [ $TARGET = thumbv7m-none-eabi ]; then
cat >>Cargo.toml <<'EOF'
[dependencies.stm32f103xx]
features = ["rt"]
version = "0.9.0"
EOF
local ex=device
cargo build --target $TARGET --example $ex
cargo build --target $TARGET --example $ex --release
examples+=( $ex )
fi
IFS=,;eval arm-none-eabi-size target/$TARGET/release/examples/"{${examples[*]}}"
popd
rm -rf $td
}
main
#!/bin/bash
cargo build --target thumbv7em-none-eabihf --release
//! How to use the heap and a dynamic memory allocator
//!
//! This example depends on the alloc-cortex-m crate so you'll have to add it to your Cargo.toml:
//!
//! ``` text
//! # or edit the Cargo.toml file manually
//! $ cargo add alloc-cortex-m
//! ```
//!
//! ---
#![feature(alloc)]
#![feature(global_allocator)]
#![feature(used)]
#![no_std]
// This is the allocator crate; you can use a different one
extern crate alloc_cortex_m;
#[macro_use]
extern crate alloc;
extern crate cortex_m;
extern crate cortex_m_rt;
extern crate cortex_m_semihosting;
extern crate panic_abort; // panicking behavior
use core::fmt::Write;
use alloc_cortex_m::CortexMHeap;
use cortex_m::asm;
use cortex_m_semihosting::hio;
#[global_allocator]
static ALLOCATOR: CortexMHeap = CortexMHeap::empty();
extern "C" {
static mut _sheap: u32;
}
const HEAP_SIZE: usize = 1024; // in bytes
fn main() {
// Initialize the allocator
let start = unsafe { &mut _sheap as *mut u32 as usize };
unsafe { ALLOCATOR.init(start, HEAP_SIZE) }
// Growable array allocated on the heap
let xs = vec![0, 1, 2];
let mut stdout = hio::hstdout().unwrap();
writeln!(stdout, "{:?}", xs).unwrap();
}
// As we are not using interrupts, we just register a dummy catch all handler
#[link_section = ".vector_table.interrupts"]
#[used]
static INTERRUPTS: [extern "C" fn(); 240] = [default_handler; 240];
extern "C" fn default_handler() {
asm::bkpt();
}
//! Debugging a crash (exception)
//!
//! The `cortex-m-rt` crate provides functionality for this through a default exception handler.
//! When an exception is hit, the default handler will trigger a breakpoint and in this debugging
//! context the stacked registers are accessible.
//!
//! In you run the example below, you'll be able to inspect the state of your program under the
//! debugger using these commands:
//!
//! ``` text
//! (gdb) # Exception frame = program state during the crash
//! (gdb) print/x *ef
//! $1 = cortex_m::exception::ExceptionFrame {
//! r0 = 0x2fffffff,
//! r1 = 0x2fffffff,
//! r2 = 0x0,
//! r3 = 0x0,
//! r12 = 0x0,
//! lr = 0x8000481,
//! pc = 0x8000460,
//! xpsr = 0x61000000,
//! }
//!
//! (gdb) # Where did we come from?
//! (gdb) backtrace
//! #0 cortex_m_rt::default_handler (ef=0x20004f54) at (..)
//! #1 <signal handler called>
//! #2 0x08000460 in core::ptr::read_volatile<u32> (src=0x2fffffff) at (..)
//! #3 0x08000480 in crash::main () at examples/crash.rs:68
//!
//! (gdb) # Nail down the location of the crash
//! (gdb) disassemble/m ef.pc
//! Dump of assembler code for function core::ptr::read_volatile<u32>:
//! 408 pub unsafe fn read_volatile<T>(src: *const T) -> T {
//! 0x08000454 <+0>: sub sp, #20
//! 0x08000456 <+2>: mov r1, r0
//! 0x08000458 <+4>: str r0, [sp, #8]
//! 0x0800045a <+6>: ldr r0, [sp, #8]
//! 0x0800045c <+8>: str r0, [sp, #12]
//!
//! 409 intrinsics::volatile_load(src)
//! 0x0800045e <+10>: ldr r0, [sp, #12]
//! 0x08000460 <+12>: ldr r0, [r0, #0]
//! 0x08000462 <+14>: str r0, [sp, #16]
//! 0x08000464 <+16>: ldr r0, [sp, #16]
//! 0x08000466 <+18>: str r1, [sp, #4]
//! 0x08000468 <+20>: str r0, [sp, #0]
//! 0x0800046a <+22>: b.n 0x800046c <core::ptr::read_volatile<u32>+24>
//!
//! 410 }
//! 0x0800046c <+24>: ldr r0, [sp, #0]
//! 0x0800046e <+26>: add sp, #20
//! 0x08000470 <+28>: bx lr
//!
//! End of assembler dump.
//! ```
//!
//! ---
#![feature(used)]
#![no_std]
extern crate cortex_m;
extern crate cortex_m_rt;
extern crate panic_abort; // panicking behavior
use core::ptr;
use cortex_m::asm;
fn main() {
// Read an invalid memory address
unsafe {
ptr::read_volatile(0x2FFF_FFFF as *const u32);
}
}
// As we are not using interrupts, we just register a dummy catch all handler
#[link_section = ".vector_table.interrupts"]
#[used]
static INTERRUPTS: [extern "C" fn(); 240] = [default_handler; 240];
extern "C" fn default_handler() {
asm::bkpt();
}
//! Using a device crate
//!
//! Crates generated using [`svd2rust`] are referred to as device crates. These crates provides an
//! API to access the peripherals of a device. When you depend on one of these crates and the "rt"
//! feature is enabled you don't need link to the cortex-m-rt crate.
//!
//! [`svd2rust`]: https://crates.io/crates/svd2rust
//!
//! Device crates also provide an `interrupt!` macro to register interrupt handlers.
//!
//! This example depends on the [`stm32f103xx`] crate so you'll have to add it to your Cargo.toml.
//!
//! [`stm32f103xx`]: https://crates.io/crates/stm32f103xx
//!
//! ```
//! $ edit Cargo.toml && tail $_
//! [dependencies.stm32f103xx]
//! features = ["rt"]
//! version = "0.9.0"
//! ```
//!
//! ---
#![deny(warnings)]
#![feature(const_fn)]
#![no_std]
extern crate cortex_m;
// extern crate cortex_m_rt; // included in the device crate
extern crate cortex_m_semihosting;
#[macro_use(exception, interrupt)]
extern crate stm32f103xx;
extern crate panic_abort; // panicking behavior
use core::cell::RefCell;
use core::fmt::Write;
use cortex_m::interrupt::{self, Mutex};
use cortex_m::peripheral::syst::SystClkSource;
use cortex_m_semihosting::hio::{self, HStdout};
use stm32f103xx::Interrupt;
static HSTDOUT: Mutex<RefCell<Option<HStdout>>> = Mutex::new(RefCell::new(None));
static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> = Mutex::new(RefCell::new(None));
fn main() {
let global_p = cortex_m::Peripherals::take().unwrap();
interrupt::free(|cs| {
let hstdout = HSTDOUT.borrow(cs);
if let Ok(fd) = hio::hstdout() {
*hstdout.borrow_mut() = Some(fd);
}
let mut nvic = global_p.NVIC;
nvic.enable(Interrupt::TIM2);
*NVIC.borrow(cs).borrow_mut() = Some(nvic);
let mut syst = global_p.SYST;
syst.set_clock_source(SystClkSource::Core);
syst.set_reload(8_000_000); // 1s
syst.enable_counter();
syst.enable_interrupt();
});
}
exception!(SYS_TICK, tick);
fn tick() {
interrupt::free(|cs| {
let hstdout = HSTDOUT.borrow(cs);
if let Some(hstdout) = hstdout.borrow_mut().as_mut() {
writeln!(*hstdout, "Tick").ok();
}
if let Some(nvic) = NVIC.borrow(cs).borrow_mut().as_mut() {
nvic.set_pending(Interrupt::TIM2);
}
});
}
interrupt!(TIM2, tock, locals: {
tocks: u32 = 0;
});
fn tock(l: &mut TIM2::Locals) {
l.tocks += 1;
interrupt::free(|cs| {
let hstdout = HSTDOUT.borrow(cs);
if let Some(hstdout) = hstdout.borrow_mut().as_mut() {
writeln!(*hstdout, "Tock ({})", l.tocks).ok();
}
});
}
//! Prints "Hello, world!" on the OpenOCD console using semihosting
//!
//! ---
#![feature(used)]
#![no_std]
extern crate cortex_m;
extern crate cortex_m_rt;
extern crate cortex_m_semihosting;
extern crate panic_abort; // panicking behavior
use core::fmt::Write;
use cortex_m::asm;
use cortex_m_semihosting::hio;
fn main() {
let mut stdout = hio::hstdout().unwrap();
writeln!(stdout, "Hello, world!").unwrap();
}
// As we are not using interrupts, we just register a dummy catch all handler
#[link_section = ".vector_table.interrupts"]