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Commit ad8379cf authored by tommy's avatar tommy Committed by Tommy Andersson
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bare6 done

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Cargo.toml
+ 4
− 0
View file @ ad8379cf
......@@ -36,6 +36,10 @@ version = "0.13.0"
features = ["stm32f411", "rt"]
# [dependencies.stm32f4]
# version = "0.13.0"
# features = ["stm32f411", "rt"]
[dependencies.stm32f4xx-hal]
version = "0.8.3"
features = ["rt", "stm32f411", "usb_fs"]
......
examples/rtic_bare5.rs
+ 0
− 4
View file @ ad8379cf
......@@ -208,10 +208,6 @@ const APP: () = {
}
};
<<<<<<< HEAD
=======
>>>>>>> 4897099 (Did my best)
// 1. C like API.
// Using C the .h files are used for defining interfaces, like function signatures (prototypes),
// structs and macros (but usually not the functions themselves).
......
examples/rtic_bare6.rs
+ 51
− 41
View file @ ad8379cf
......@@ -17,9 +17,11 @@ use stm32f4xx_hal::{
prelude::*,
stm32::{self, GPIOC, RCC},
};
//original
const OFFSET: u32 = 8_000_000;
//const OFFSET: u32 = 24_000_000;
#[rtic::app(device = stm32f4xx_hal::stm32, monotonic = rtic::cyccnt::CYCCNT, peripherals = true)]
const APP: () = {
struct Resources {
......@@ -55,29 +57,32 @@ const APP: () = {
let rcc = device.RCC.constrain();
let _clocks = rcc.cfgr.freeze();
// let _clocks = rcc.cfgr.freeze();
// Set up the system clock. 48 MHz?
// let _clocks = rcc
// .cfgr
// .sysclk(48.mhz())
// .pclk1(24.mhz())
// .freeze();
// let _clocks = rcc
// .cfgr
// .sysclk(64.mhz())
// .pclk1(64.mhz())
// .pclk2(64.mhz())
// .freeze();
//
// let _clocks = rcc
// .cfgr
// .sysclk(84.mhz())
// .pclk1(42.mhz())
// .pclk2(64.mhz())
// .freeze();
let _clocks = rcc
.cfgr
.sysclk(48.mhz())
.pclk1(24.mhz())
.freeze();
/*
let _clocks = rcc
.cfgr
.sysclk(64.mhz())
.pclk1(64.mhz())
.pclk2(64.mhz())
.freeze();
*/
/*
let _clocks = rcc
.cfgr
.sysclk(84.mhz())
.pclk1(42.mhz())
.pclk2(64.mhz())
.freeze();
*/
// pass on late resources
init::LateResources {
GPIOA: device.GPIOA,
......@@ -119,10 +124,10 @@ const APP: () = {
fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
// output MCO2 to pin PC9
// mco2 : SYSCLK = 0b00
//mco2 : SYSCLK = 0b00;
// mcopre : divide by 4 = 0b110
rcc.cfgr
.modify(|_, w| unsafe { w.mco2().bits(0b00).mco2pre().bits(0b110) });
.modify(|_, w| unsafe { w.mco2().sysclk().mco2pre().div4() });
// power on GPIOC, RM0368 6.3.11
rcc.ahb1enr.modify(|_, w| w.gpiocen().set_bit());
......@@ -132,12 +137,12 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
// AF0, gpioc reset value = AF0
// configure PC9 as alternate function 0b10, RM0368 6.2.10
gpioc.moder.modify(|_, w| w.moder9().bits(0b10));
gpioc.moder.modify(|_, w| w.moder9().alternate());
// otyper reset state push/pull, in reset state (don't need to change)
// ospeedr 0b11 = very high speed
gpioc.ospeedr.modify(|_, w| w.ospeedr9().bits(0b11));
gpioc.ospeedr.modify(|_, w| w.ospeedr9().medium_speed());
}
// 0. Background reading:
......@@ -202,7 +207,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// `rcc.cfgr.sysclk(64.mhz()).pclk1(64.mhz()).pclk2(64.mhz()).freeze()`;
//
// ** your answer here **
// pclk1 is restricted to not run faster than 48 mHz
//
// `rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();`
//
......@@ -217,7 +222,8 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// What happens?
//
// ** your answer here **
// I get the error "Frequency searched for is out of range for this VOS range
// when changing PCLK1 from 32 to 64
//
// Try to setup the clock according to:
//
......@@ -225,7 +231,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// `rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();`
//
// ** your answer here **
// When I chnage pclk2 to 64 the other sysclk chnages to 64 and pclk1 changes to 32.
//
// Commit your answers (bare6_0)
//
......@@ -237,7 +243,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// What is the (default) MCU (SYSCLK) frequency?
//
// ** your answer here **
// 16 Mhz
//
// What is the (default) DWT CYCCNT frequency?
//
......@@ -245,7 +251,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// What is the frequency of blinking?
//
// ** your answer here **
// 1 Hz
//
// Commit your answers (bare6_1)
//
......@@ -254,11 +260,11 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// Compute the value of SYSCLK based on the oscilloscope reading
//
// ** your answer here **
// 3.91 MHz
//
// What is the peak to peak (voltage) reading of the signal?
//
// ** your answer here **
// 5.4 - 5.6 V or 4.7 - 4.8 V
//
// Make a folder called "pictures" in your git project.
// Make a screen dump or photo of the oscilloscope output.
......@@ -271,7 +277,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//`
// What is the frequency of blinking?
//
// ** your answer here **
// 3 Hz (ociloscope: 11.9 MHz or 12 MHz)
//
// Now change the constant `OFFSET` so you get the same blinking frequency as in 1.
// Test and validate that you got the desired behavior.
......@@ -282,15 +288,15 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// What is the frequency of MCO2 read by the oscilloscope?
//
// ** your answer here **
// 12 MHz
//
// Compute the value of SYSCLK based on the oscilloscope reading.
//
// ** your answer here **
// 12 * 4 = 48 MHz (roughly rounded)
//
// What is the peak to peak reading of the signal?
//
// ** your answer here **
// 4.9 V
//
// Make a screen dump or photo of the oscilloscope output.
// Save the the picture as "bare_6_48mhz_high_speed".
......@@ -325,11 +331,13 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// Did the frequency change in comparison to assignment 5?
//
// ** your answer here **
// No. It is the same.
//
// What is the peak to peak reading of the signal (and why did it change)?
//
// ** your answer here **
// 3.58 - 3.6 V. Since the speed of the signal is lowered the the amount af volt will be lowered since the
// duty scycle is reduced. If we increase the speed further the volt increas and decrease if the speed is even
// lowered.
//
// Make a screen dump or photo of the oscilloscope output.
// Save the the picture as "bare_6_48mhz_low_speed".
......@@ -342,11 +350,11 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// Does the code compile?
//
// ** your answer here **
// Yes, but it panics.
//
// What happens at run-time?
//
// ** your answer here **
// It panics.
//
// Try setting the clocks according to:
//
......@@ -354,14 +362,16 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// Does the code compile?
//
// ** your answer here **
// Yes.
//
// What happens at run-time?
//
// ** your answer here **
// It runs.
//
// Is that a correct?
//
// Yes, I suppose?
//
// Optional: If you find it incorrect, file an issue to `stm32f4xx-hal` describing the problem.
// (Remember always check already open issues, and add to existing if related.)
//
......
examples/rtic_bare7.rs
+ 9
− 4
View file @ ad8379cf
......@@ -17,7 +17,7 @@ use stm32f4xx_hal::{
gpio::{gpioa::PA5, Output, PushPull},
prelude::*,
};
;
use embedded_hal::digital::v2::{OutputPin, ToggleableOutputPin};
const OFFSET: u32 = 8_000_000;
......@@ -27,7 +27,8 @@ const APP: () = {
struct Resources {
// late resources
GPIOA: stm32::GPIOA,
// led: PA5<Output<PushPull>>,
led: PA5<Output<PushPull>>,
}
#[init(schedule = [toggle])]
fn init(cx: init::Context) -> init::LateResources {
......@@ -37,6 +38,7 @@ const APP: () = {
let mut core = cx.core;
let device = cx.device;
// Initialize (enable) the monotonic timer (CYCCNT)
core.DCB.enable_trace();
core.DWT.enable_cycle_counter();
......@@ -50,15 +52,18 @@ const APP: () = {
// power on GPIOA, RM0368 6.3.11
device.RCC.ahb1enr.modify(|_, w| w.gpioaen().set_bit());
// configure PA5 as output, RM0368 8.4.1
// configure PA5 as output, 8.4.1
device.GPIOA.moder.modify(|_, w| w.moder5().bits(1));
// pass on late resources
init::LateResources {
GPIOA: device.GPIOA,
led: ,
}
}
#[idle]
fn idle(_cx: idle::Context) -> ! {
rprintln!("idle");
......@@ -67,7 +72,7 @@ const APP: () = {
}
}
#[task(resources = [GPIOA], schedule = [toggle])]
#[task(resources = [led], schedule = [toggle])]
fn toggle(cx: toggle::Context) {
static mut TOGGLE: bool = false;
rprintln!("toggle @ {:?}", Instant::now());
......
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