bare6_2

examples/rtic_bare6.rs

@@ -206,7 +206,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 //
 //    `rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();`
 //
-//      I guess that there should be some kind of divission factor between pcklk1 and 2 or something
+//      It works as it should
 //
 //    Start `stm32cubemx` and select or create a project targeting stm32f401.
 //    Go to the graphical clock configuration view.
@@ -252,11 +252,11 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
 //
 //    Compute the value of SYSCLK based on the oscilloscope reading
 //
-//    ** your answer here **
+//      15.2MHz (Acording to the picture. It bounced between 3.8-4.2, so around 16MHz)
 //
 //    What is the peak to peak (voltage) reading of the signal?
 //
-//    ** your answer here **
+//      4.8V
 //
 //    Make a folder called "pictures" in your git project.
 //    Make a screen dump or photo of the oscilloscope output.