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rtt_rtic_i2c.rs

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  • Forked from Per Lindgren / e7020e_2021
    Source project has a limited visibility.
    rtt_rtic_i2c.rs 5.79 KiB
    //! cargo run --examples rtt-pwm
    
    #![deny(unsafe_code)]
    // #![deny(warnings)]
    #![no_main]
    #![no_std]
    
    use cortex_m::asm::delay;
    use panic_halt as _;
    use rtt_target::{rprintln, rtt_init_print};
    
    use stm32f4xx_hal::{
        gpio::{
            gpiob::{PB8, PB9},
            gpioc::PC13,
            AlternateOD, Edge, ExtiPin, Input, PullUp, Speed, AF4,
        },
        i2c::I2c,
        prelude::*,
        stm32::I2C1,
    };
    
    #[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true)]
    const APP: () = {
        #[init]
        fn init(cx: init::Context) {
            rtt_init_print!();
            rprintln!("init");
            let dp = cx.device;
    
            // Set up the system clock, 48MHz
            let rcc = dp.RCC.constrain();
            // let clocks = rcc.cfgr.sysclk(48.mhz()).freeze();
            let clocks = rcc.cfgr.freeze();
            // let clocks = rcc
            //     .cfgr
            //     .hclk(48.mhz())
            //     .sysclk(48.mhz())
            //     .pclk1(24.mhz())
            //     .pclk2(24.mhz())
            //     .freeze();
    
            // Set up I2C.
            let gpiob = dp.GPIOB.split();
            let scl = gpiob.pb8.into_alternate_af4().set_open_drain();
            let sda = gpiob.pb9.into_alternate_af4().set_open_drain();
            let mut i2c = I2c::i2c1(dp.I2C1, (scl, sda), 400.khz(), clocks);
    
            rprintln!("here");
    
            // configure
            // 7:6 -     reserved
            // 5   ORDER logic 0, the MSB of the data word is transmitted first.
            //           logic 1, the LSB of the data word is transmitted first.
            // 4   -     reserved
            // 3:3 M1:M0 Mode selection
            //           00 - SPICLK LOW when idle; data clocked in on leading edge (CPOL = 0, CPHA = 0)
            //           01 - SPICLK LOW when idle; data clocked in on trailing edge (CPOL = 0, CPHA = 1)
            //           10 - SPICLK HIGH when idle; data clocked in on trailing edge (CPOL = 1, CPHA = 0)
            //           11 - SPICLK HIGH when idle; data clocked in on leading edge (CPOL = 1, CPHA = 1)
            // 1:0 F1:F0 SPI clock rate
            //           00 - 1843 kHz
            //           01 - 461 kHz
            //           10 - 115 kHz
            //           11 - 58 kHz
    
            let i2c_addr = 0x50 >> 1;
            let i2c_command_conf = 0xF0;
    
            let i2c_conf_reg = (0b0 << 5) /* MSB First */ |