Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
E
e7020e_2019
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Henrik Theolin
e7020e_2019
Commits
1f563c4e
Commit
1f563c4e
authored
6 years ago
by
Henrik Theolin
Browse files
Options
Downloads
Patches
Plain Diff
bare4_3
parent
8a1f801e
Branches
Branches containing commit
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
examples/bare4.rs
+9
-5
9 additions, 5 deletions
examples/bare4.rs
with
9 additions
and
5 deletions
examples/bare4.rs
+
9
−
5
View file @
1f563c4e
...
...
@@ -39,8 +39,8 @@ use address::*;
#[inline(always)]
fn
read_u32
(
addr
:
u32
)
->
u32
{
//
unsafe { core::ptr::read_volatile(addr as *const _) }
core
::
ptr
::
read_volatile
(
addr
as
*
const
_
)
unsafe
{
core
::
ptr
::
read_volatile
(
addr
as
*
const
_
)
}
//
core::ptr::read_volatile(addr as *const _)
}
#[inline(always)]
...
...
@@ -128,16 +128,20 @@ fn main() -> ! {
//
// Why is it important that ordering of volatile operations are ensured by the compiler?
//
// ** your answer here **
// ** Variable used by volatile operations may change between accesses,
// reordering might introduce undefined or unexpected behaviour,
// if a read is ordered before a write the value would alter and not return the expected,
// or if reading from a register is performed before that register is set as read. **
//
// Give an example in the above code, where reordering might make things go horribly wrong
// (hint, accessing a peripheral not being powered...)
//
// ** your answer here **
// ** Read or write to GPIOA_BSRR before GPIOA_MODER is set to output,
// doing anything before setting RCC_AHB1ENR would be bad **
//
// Without the non-reording proprety of `write_volatile/read_volatile` could that happen in theory
// (argue from the point of data dependencies).
//
// **
your answer here
**
// **
Writing/Reading in wrong order would result in unexpexed results.
**
//
// Commit your answers (bare4_3)
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment