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Commits on Source 21

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with 711 additions and 126 deletions
.vscode/.cortex-debug.peripherals.state.json 0 → 100644
View file @ 19008d4f
[]
\ No newline at end of file
.vscode/.cortex-debug.registers.state.json 0 → 100644
View file @ 19008d4f
[]
\ No newline at end of file
.vscode/launch.json
View file @ 19008d4f
...@@ -16,9 +16,9 @@ ...@@ -16,9 +16,9 @@
"preLaunchTask": "cargo build", "preLaunchTask": "cargo build",
"executable": "./target/thumbv7em-none-eabihf/debug/app", "executable": "./target/thumbv7em-none-eabihf/debug/app",
"configFiles": [ "configFiles": [
"interface/stlink.cfg", //"interface/stlink.cfg",
// "interface/stlink-v2-1.cfg", // deprecated setup script "interface/stlink-v2-1.cfg", // deprecated setup script
"target/stm32f4x.cfg" // "target/stm32f4x.cfg"
], ],
"postLaunchCommands": [ "postLaunchCommands": [
"monitor arm semihosting enable" "monitor arm semihosting enable"
...@@ -39,9 +39,9 @@ ...@@ -39,9 +39,9 @@
"preLaunchTask": "cargo build --example", "preLaunchTask": "cargo build --example",
"executable": "./target/thumbv7em-none-eabihf/debug/examples/${fileBasenameNoExtension}", "executable": "./target/thumbv7em-none-eabihf/debug/examples/${fileBasenameNoExtension}",
"configFiles": [ "configFiles": [
"interface/stlink.cfg", //"interface/stlink.cfg",
// "interface/stlink-v2-1.cfg", // deprecated setup script "interface/stlink-v2-1.cfg", // deprecated setup script
"target/stm32f4x.cfg" // "target/stm32f4x.cfg"
], ],
"postLaunchCommands": [ "postLaunchCommands": [
"monitor arm semihosting enable", "monitor arm semihosting enable",
...@@ -76,8 +76,8 @@ ...@@ -76,8 +76,8 @@
"executable": "./target/thumbv7em-none-eabihf/debug/examples/${fileBasenameNoExtension}", "executable": "./target/thumbv7em-none-eabihf/debug/examples/${fileBasenameNoExtension}",
"configFiles": [ "configFiles": [
"interface/stlink.cfg", "interface/stlink.cfg",
// "interface/stlink-v2-1.cfg", // deprecated setup script "interface/stlink-v2-1.cfg", // deprecated setup script
"target/stm32f4x.cfg" // "target/stm32f4x.cfg"
], ],
"postLaunchCommands": [ "postLaunchCommands": [
"monitor arm semihosting enable", "monitor arm semihosting enable",
...@@ -101,8 +101,8 @@ ...@@ -101,8 +101,8 @@
"executable": "./target/thumbv7em-none-eabihf/debug/examples/${fileBasenameNoExtension}", "executable": "./target/thumbv7em-none-eabihf/debug/examples/${fileBasenameNoExtension}",
"configFiles": [ "configFiles": [
"interface/stlink.cfg", "interface/stlink.cfg",
// "interface/stlink-v2-1.cfg", // deprecated setup script "interface/stlink-v2-1.cfg", // deprecated setup script
"target/stm32f4x.cfg" // "target/stm32f4x.cfg"
], ],
"postLaunchCommands": [ "postLaunchCommands": [
"monitor arm semihosting enable", "monitor arm semihosting enable",
...@@ -125,9 +125,9 @@ ...@@ -125,9 +125,9 @@
"preLaunchTask": "cargo build --example --features rtfm", "preLaunchTask": "cargo build --example --features rtfm",
"executable": "./target/thumbv7em-none-eabihf/debug/examples/${fileBasenameNoExtension}", "executable": "./target/thumbv7em-none-eabihf/debug/examples/${fileBasenameNoExtension}",
"configFiles": [ "configFiles": [
"interface/stlink.cfg", //"interface/stlink.cfg",
// "interface/stlink-v2-1.cfg", // deprecated setup script "interface/stlink-v2-1.cfg", // deprecated setup script
"target/stm32f4x.cfg" // "target/stm32f4x.cfg"
], ],
"postLaunchCommands": [ "postLaunchCommands": [
"monitor arm semihosting enable", "monitor arm semihosting enable",
...@@ -150,9 +150,9 @@ ...@@ -150,9 +150,9 @@
"preLaunchTask": "cargo build --example --release", "preLaunchTask": "cargo build --example --release",
"executable": "./target/thumbv7em-none-eabihf/release/examples/${fileBasenameNoExtension}", "executable": "./target/thumbv7em-none-eabihf/release/examples/${fileBasenameNoExtension}",
"configFiles": [ "configFiles": [
"interface/stlink.cfg", //"interface/stlink.cfg",
// "interface/stlink-v2-1.cfg", // deprecated setup script "interface/stlink-v2-1.cfg", // deprecated setup script
"target/stm32f4x.cfg" // "target/stm32f4x.cfg"
], ],
"postLaunchCommands": [ "postLaunchCommands": [
"monitor arm semihosting enable", "monitor arm semihosting enable",
...@@ -175,9 +175,9 @@ ...@@ -175,9 +175,9 @@
"preLaunchTask": "cargo build --example --release --features stm32f4", "preLaunchTask": "cargo build --example --release --features stm32f4",
"executable": "./target/thumbv7em-none-eabihf/release/examples/${fileBasenameNoExtension}", "executable": "./target/thumbv7em-none-eabihf/release/examples/${fileBasenameNoExtension}",
"configFiles": [ "configFiles": [
"interface/stlink.cfg", //"interface/stlink.cfg",
// "interface/stlink-v2-1.cfg", // deprecated setup script "interface/stlink-v2-1.cfg", // deprecated setup script
"target/stm32f4x.cfg" // "target/stm32f4x.cfg"
], ],
"postLaunchCommands": [ "postLaunchCommands": [
"monitor reset init", // sets the MCU to 64MHz "monitor reset init", // sets the MCU to 64MHz
......
Cargo.lock 0 → 100644
View file @ 19008d4f
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Cargo.toml
View file @ 19008d4f
...@@ -21,7 +21,7 @@ heapless = "0.5.3" ...@@ -21,7 +21,7 @@ heapless = "0.5.3"
[dependencies.cortex-m] [dependencies.cortex-m]
version = "0.6.2" version = "0.6.2"
# features = ["inline-asm"] # <- currently requires nightly compiler features = ["inline-asm"] # <- currently requires nightly compiler
[dependencies.cortex-m-rt] [dependencies.cortex-m-rt]
version = "0.6.12" version = "0.6.12"
......
examples/bare0.rs
View file @ 19008d4f
...@@ -22,25 +22,40 @@ use panic_semihosting as _; ...@@ -22,25 +22,40 @@ use panic_semihosting as _;
use cortex_m_rt::entry; use cortex_m_rt::entry;
// a constant (cannot be changed at run-time) // a constant (cannot be changed at run-time)
const X_INIT: u32 = 10; //const X_INIT: u32 = 10;
// const X_INIT: u32 = core::u32::MAX; const X_INIT: u32 = core::u32::MAX;
// global mutable variables (changed using unsafe code) // global mutable variables (changed using unsafe code)
static mut X: u32 = X_INIT; static mut X: u32 = X_INIT;
static mut Y: u32 = 0; static mut Y: u32 = 0;
fn read_x()->u32{
unsafe{X}
}
fn read_y()->u32{
unsafe{Y}
}
fn write_y(y:u32){
unsafe{Y=y};
}
fn write_x(x:u32){
unsafe{X=x};
}
#[entry] #[entry]
fn main() -> ! { fn main() -> ! {
// local mutable variable (changed in safe code) // local mutable variable (changed in safe code)
let mut x = unsafe { X }; let mut x = read_x();
loop { loop {
x += 1; // <- place breakpoint here (3) x = x.wrapping_add(1); // <- place breakpoint here (3)
unsafe {
X += 1; write_x(read_x().wrapping_add(1));
Y = X; write_y(read_x());
assert!(x == X && X == Y); assert!(x == read_x() && read_x() == read_y()+1);
}
} }
} }
...@@ -57,17 +72,22 @@ fn main() -> ! { ...@@ -57,17 +72,22 @@ fn main() -> ! {
// Look under Variables/Local what do you find. // Look under Variables/Local what do you find.
// //
// ** your answer here ** // ** your answer here **
// local
// x: 4685359
// //
// In the Expressions (WATCH -vscode) view add X and Y // In the Expressions (WATCH -vscode) view add X and Y
// what do you find // what do you find
// //
// ** your answer here ** // ** your answer here **
// // X: 4685359
// Y: <optimized out>
// Step through one complete iteration of the loop // Step through one complete iteration of the loop
// and see how the (Local) Variables are updated // and see how the (Local) Variables are updated
// can you foresee what will eventually happen? // can you foresee what will eventually happen?
// //
// ** place your answer here ** // ** place your answer here **
// Its inceremented by one each iteration and it will eventually wrap.
// //
// Commit your answers (bare0_1) // Commit your answers (bare0_1)
// //
...@@ -76,6 +96,8 @@ fn main() -> ! { ...@@ -76,6 +96,8 @@ fn main() -> ! {
// (Hint, look under OUTPUT/Adopter Output to see the `openocd` output.) // (Hint, look under OUTPUT/Adopter Output to see the `openocd` output.)
// //
// ** your answer here ** // ** your answer here **
// First it says that the local x gets optimized out then it panics
// "panicked at 'attempt to add with overflow', examples/bare0.rs:42:9"
// //
// Commit your answers (bare0_2) // Commit your answers (bare0_2)
// //
...@@ -84,10 +106,10 @@ fn main() -> ! { ...@@ -84,10 +106,10 @@ fn main() -> ! {
// Change (both) += operations to use wrapping_add // Change (both) += operations to use wrapping_add
// load and run the program, what happens // load and run the program, what happens
// ** your answer here ** // ** your answer here **
// // x wraps around and becomes 0 and X doesnt change
// Now continue execution, what happens // Now continue execution, what happens
// ** your answer here ** // ** your answer here **
// // x continues to get bigger X is still the same
// Commit your answers (bare0_3) // Commit your answers (bare0_3)
// //
// (If the program did not succeed back to the breakpoint // (If the program did not succeed back to the breakpoint
...@@ -96,7 +118,7 @@ fn main() -> ! { ...@@ -96,7 +118,7 @@ fn main() -> ! {
// 4. Change the assertion to `assert!(x == X && X == Y + 1)`, what happens? // 4. Change the assertion to `assert!(x == X && X == Y + 1)`, what happens?
// //
// ** place your answer here ** // ** place your answer here **
// // the program panics "panicked at 'assertion failed: x == X && X == Y + 1', examples/bare0.rs:45:13"
// Commit your answers (bare0_4) // Commit your answers (bare0_4)
// //
// 5. Remove the assertion and implement "safe" functions for // 5. Remove the assertion and implement "safe" functions for
......
examples/bare1.rs
View file @ 19008d4f
...@@ -24,9 +24,9 @@ fn main() -> ! { ...@@ -24,9 +24,9 @@ fn main() -> ! {
cortex_m::asm::bkpt(); cortex_m::asm::bkpt();
// prevent optimization by read-volatile (unsafe) // prevent optimization by read-volatile (unsafe)
unsafe { // unsafe {
core::ptr::read_volatile(&x); // core::ptr::read_volatile(&x);
} // }
} }
} }
...@@ -59,10 +59,12 @@ fn main() -> ! { ...@@ -59,10 +59,12 @@ fn main() -> ! {
// (passing 3 breakpoints) // (passing 3 breakpoints)
// //
// ** your answer here ** // ** your answer here **
// // The program panicsc
// What is the `ITM` output. // What is the `ITM` output.
// //
// ** your answer here ** // ** your answer here **
// panicked at 'attempt to add with overflow', examples/bare1.rs:23:9
// //
// Commit your answer (bare1_1) // Commit your answer (bare1_1)
// //
...@@ -73,18 +75,58 @@ fn main() -> ! { ...@@ -73,18 +75,58 @@ fn main() -> ! {
// //
// What is the output of: // What is the output of:
// > disassemble // > disassemble
//
// ** your answer here ** // ** your answer here **
// //
// (gdb) disassemble
// Dump of assembler code for function bare1::__cortex_m_rt_main:
// 0x0800040a <+0>: push {r7, lr}
// 0x0800040c <+2>: mov r7, sp
// 0x0800040e <+4>: sub sp, #16
// 0x08000410 <+6>: mvn.w r0, #1
// 0x08000414 <+10>: str r0, [sp, #8]
// 0x08000416 <+12>: movs r0, #0
// 0x08000418 <+14>: strb.w r0, [sp, #12]
// 0x0800041c <+18>: ldr r0, [sp, #8]
// 0x0800041e <+20>: str r0, [sp, #4]
// 0x08000420 <+22>: b.n 0x8000422 <bare1::__cortex_m_rt_main+24>
// => 0x08000422 <+24>: bkpt 0x0000
// 0x08000424 <+26>: b.n 0x8000426 <bare1::__cortex_m_rt_main+28>
// ---Type <return> to continue, or q <return> to quit---
// 0x08000426 <+28>: ldr r0, [sp, #4]
// 0x08000428 <+30>: adds r1, r0, #1
// 0x0800042a <+32>: mov r2, r1
// 0x0800042c <+34>: cmp r1, r0
// 0x0800042e <+36>: str r2, [sp, #0]
// 0x08000430 <+38>: bcc.n 0x8000446 <bare1::__cortex_m_rt_main+60>
// 0x08000432 <+40>: b.n 0x8000434 <bare1::__cortex_m_rt_main+42>
// 0x08000434 <+42>: ldr r0, [sp, #0]
// 0x08000436 <+44>: str r0, [sp, #4]
// 0x08000438 <+46>: bkpt 0x0000
// 0x0800043a <+48>: b.n 0x800043c <bare1::__cortex_m_rt_main+50>
// 0x0800043c <+50>: add r0, sp, #4
// 0x0800043e <+52>: bl 0x800045e <core::ptr::read_volatile>
// 0x08000442 <+56>: b.n 0x8000444 <bare1::__cortex_m_rt_main+58>
// 0x08000444 <+58>: b.n 0x8000422 <bare1::__cortex_m_rt_main+24>
// 0x08000446 <+60>: movw r0, #9520 ; 0x2530
// ---Type <return> to continue, or q <return> to quit---
// 0x0800044a <+64>: movt r0, #2048 ; 0x800
// 0x0800044e <+68>: movw r2, #9492 ; 0x2514
// 0x08000452 <+72>: movt r2, #2048 ; 0x800
// 0x08000456 <+76>: movs r1, #28
// 0x08000458 <+78>: bl 0x80008ec <core::panicking::panic>
// 0x0800045c <+82>: udf #254 ; 0xfe
// End of assembler dump.
// How many instructions are in between the two `bkpt` instructions in the loop. // How many instructions are in between the two `bkpt` instructions in the loop.
// Notice, the generated code may not be exactly what you expect :) // Notice, the generated code may not be exactly what you expect :)
// //
// ** your answer here ** // ** your answer here **
// 10
// //
// Which instruction stores the local variable on the stack. // Which instruction stores the local variable on the stack.
// //
// ** your answer here ** // ** your answer here **
// //
// 0x0800040a <+0>: push {r7, lr}
// Commit your answers (bare1_2) // Commit your answers (bare1_2)
// //
// 3. Release mode (optimized builds). // 3. Release mode (optimized builds).
...@@ -101,18 +143,33 @@ fn main() -> ! { ...@@ -101,18 +143,33 @@ fn main() -> ! {
// //
// ** your answer here ** // ** your answer here **
// //
// Dump of assembler code for function bare1::__cortex_m_rt_main:
// 0x0800040a <+0>: sub sp, #4
// 0x0800040c <+2>: mvn.w r0, #1
// 0x08000410 <+6>: str r0, [sp, #0]
// 0x08000412 <+8>: adds r0, #1
// => 0x08000414 <+10>: bkpt 0x0000
// 0x08000416 <+12>: str r0, [sp, #0]
// 0x08000418 <+14>: bkpt 0x0000
// 0x0800041a <+16>: ldr r0, [sp, #0]
// 0x0800041c <+18>: b.n 0x8000412 <bare1::__cortex_m_rt_main+8>
// End of assembler dump.
// How many instructions are in between the two `bkpt` instructions. // How many instructions are in between the two `bkpt` instructions.
// //
// ** your answer here ** // ** your answer here **
// // 1
// Where is the local variable stored? // Where is the local variable stored?
// //
// ** your answer here ** // ** your answer here **
// 0x08000410 <+6>: str r0, [sp, #0]
// //
// Is there now any reference to the panic handler? // Is there now any reference to the panic handler?
// If not, why is that the case? // If not, why is that the case?
// //
// ** your answer here ** // ** your answer here **
// No there is not any refrence to the panic handler
// Because in release mode rust does not include checks for
// integer overflow. If overflow occurs it just wrapps with twos complement.
// //
// commit your answers (bare1_3) // commit your answers (bare1_3)
// //
...@@ -149,15 +206,28 @@ fn main() -> ! { ...@@ -149,15 +206,28 @@ fn main() -> ! {
// //
// ** your answer here ** // ** your answer here **
// //
// Dump of assembler code for function bare1::__cortex_m_rt_main:
// 0x0800040a <+0>: bkpt 0x0000
// => 0x0800040c <+2>: bkpt 0x0000
// 0x0800040e <+4>: b.n 0x800040a <bare1::__cortex_m_rt_main>
// End of assembler dump
//
// How many instructions are in between the two `bkpt` instructions. // How many instructions are in between the two `bkpt` instructions.
// //
// ** your answer here ** // ** your answer here **
// 0
// //
// Where is the local variable stored? // Where is the local variable stored?
// What happened, and why is Rust + LLVM allowed to do that? // What happened, and why is Rust + LLVM allowed to do that?
// //
// ** your answer here ** // ** your answer here **
// //
// 0x0800040e <+4>: b.n 0x800040a <bare1::__cortex_m_rt_main>
//
// In release mode the program is the most optimized
// which means that the compiler can remove instructions that arent necessary
//
//
// commit your answers (bare1_4) // commit your answers (bare1_4)
// //
// //
......
examples/bare2.rs
View file @ 19008d4f
...@@ -78,18 +78,27 @@ fn main() -> ! { ...@@ -78,18 +78,27 @@ fn main() -> ! {
// What is the output in the ITM console? // What is the output in the ITM console?
// //
// ** your answer here ** // ** your answer here **
// // bare2
// Start 45
// End 561000215
// Diff 561000170
// Rebuild and run in release mode // Rebuild and run in release mode
// //
// > cargo build --example bare2 --release // > cargo build --example bare2 --release
// //
// ** your answer here ** // ** your answer here **
// bare2
// Start 2539927876
// End 2543927884
// Diff 4000008
// //
// Compute the ratio between debug/release optimized code // Compute the ratio between debug/release optimized code
// (the speedup). // (the speedup).
// //
// ** your answer here ** // ** your answer here **
// // start : 1.77 *10⁻8
// End : 45.35
// diff: 140.25
// commit your answers (bare2_1) // commit your answers (bare2_1)
// //
// 3. *Optional // 3. *Optional
......
examples/bare3.rs
View file @ 19008d4f
...@@ -18,26 +18,30 @@ use cortex_m_semihosting::{hprint, hprintln}; ...@@ -18,26 +18,30 @@ use cortex_m_semihosting::{hprint, hprintln};
#[entry] #[entry]
fn main() -> ! { fn main() -> ! {
hprintln!("bare3").unwrap(); hprintln!("bare3").unwrap();
let s = "ABCD"; let s: &str = "ABCD";
let bs = s.as_bytes(); let bs: &[u8] = s.as_bytes();
hprintln!("s = {}", s).unwrap(); hprintln!("s = {}", s).unwrap();
hprintln!("bs = {:?}", bs).unwrap(); hprintln!("bs = {:?}", bs).unwrap();
hprintln!("iterate over slice").unwrap(); hprintln!("iterate over slice").unwrap();
let c: &u8;
for c in bs { for c in bs {
hprint!("{},", c).unwrap(); hprint!("{},", c).unwrap();
} }
hprintln!("iterate iterate using (raw) indexing").unwrap(); hprintln!("iterate iterate using (raw) indexing").unwrap();
let i: usize;
for i in 0..s.len() { for i in 0..s.len() {
hprintln!("{},", bs[i]).unwrap(); hprintln!("{},", bs[i]).unwrap();
} }
hprintln!("").unwrap(); hprintln!("").unwrap();
let a = [65u8; 4]; let a: [u8;4] = [65u8; 4];
// let mut a = [0u8; 4]; let mut a = [0u8; 4];
let mut a = &bs[..];
hprintln!("").unwrap(); hprintln!("").unwrap();
hprintln!("a = {}", core::str::from_utf8(&a).unwrap()).unwrap(); hprintln!("a = {}", core::str::from_utf8(&a).unwrap()).unwrap();
...@@ -55,27 +59,40 @@ fn main() -> ! { ...@@ -55,27 +59,40 @@ fn main() -> ! {
// 1. What is the output in the `openocd` (Adapter Output) console? // 1. What is the output in the `openocd` (Adapter Output) console?
// //
// ** your answer here ** // ** your answer here **
// s = ABCD
// bs = [65, 66, 67, 68]
// iterate over slice
// 65,66,67,68,iterate iterate using (raw) indexing
// 65,
// 66,
// 67,
// 68,
//
// //
// a = AAAA
// What is the type of `s`? // What is the type of `s`?
// //
// ** your answer here ** // ** your answer here **
// &str
// //
// What is the type of `bs`? // What is the type of `bs`?
// //
// ** your answer here ** // ** your answer here **
// // &[u8]
// What is the type of `c`? // What is the type of `c`?
//
// ** your answer here ** // ** your answer here **
// &u8
// //
// What is the type of `a`? // What is the type of `a`?
// //
// ** your answer here ** // ** your answer here **
// array [u8;4]
// //
// What is the type of `i`? // What is the type of `i`?
// //
// ** your answer here ** // ** your answer here **
// // usize
// Commit your answers (bare3_1) // Commit your answers (bare3_1)
// //
// 2. Make types of `s`, `bs`, `c`, `a`, `i` explicit. // 2. Make types of `s`, `bs`, `c`, `a`, `i` explicit.
...@@ -87,6 +104,10 @@ fn main() -> ! { ...@@ -87,6 +104,10 @@ fn main() -> ! {
// Run the program, what happens and why? // Run the program, what happens and why?
// //
// ** your answer here ** // ** your answer here **
// The output for a is:
// a =
// a is an array of zeros and when its printed it takes the ascii value of 0
// which is null so it doesnt print anything
// //
// Commit your answers (bare3_3) // Commit your answers (bare3_3)
// //
......
examples/bare4.rs
View file @ 19008d4f
...@@ -36,8 +36,8 @@ use address::*; ...@@ -36,8 +36,8 @@ use address::*;
#[inline(always)] #[inline(always)]
fn read_u32(addr: u32) -> u32 { fn read_u32(addr: u32) -> u32 {
unsafe { core::ptr::read_volatile(addr as *const _) } // unsafe { core::ptr::read_volatile(addr as *const _) }
//core::ptr::read_volatile(addr as *const _) core::ptr::read_volatile(addr as *const _)
} }
#[inline(always)] #[inline(always)]
...@@ -56,10 +56,12 @@ fn wait(i: u32) { ...@@ -56,10 +56,12 @@ fn wait(i: u32) {
#[entry] #[entry]
fn main() -> ! { fn main() -> ! {
// power on GPIOA // power on GPIOA
//6.3.9
let r = read_u32(RCC_AHB1ENR); // read let r = read_u32(RCC_AHB1ENR); // read
write_u32(RCC_AHB1ENR, r | 1); // set enable write_u32(RCC_AHB1ENR, r | 1); // set enable
// configure PA5 as output // configure PA5 as output
//8.4.1
let r = read_u32(GPIOA_MODER) & !(0b11 << (5 * 2)); // read and mask let r = read_u32(GPIOA_MODER) & !(0b11 << (5 * 2)); // read and mask
write_u32(GPIOA_MODER, r | 0b01 << (5 * 2)); // set output mode write_u32(GPIOA_MODER, r | 0b01 << (5 * 2)); // set output mode
...@@ -68,6 +70,7 @@ fn main() -> ! { ...@@ -68,6 +70,7 @@ fn main() -> ! {
loop { loop {
// set PA5 high // set PA5 high
//8.4.7
write_u32(GPIOA_BSRR, 1 << 5); // set bit, output hight (turn on led) write_u32(GPIOA_BSRR, 1 << 5); // set bit, output hight (turn on led)
wait(10_000); wait(10_000);
...@@ -85,6 +88,7 @@ fn main() -> ! { ...@@ -85,6 +88,7 @@ fn main() -> ! {
// 1. Did you enjoy the blinking? // 1. Did you enjoy the blinking?
// //
// ** your answer here ** // ** your answer here **
// yes
// //
// Now lookup the data-sheets, and read each section referred, // Now lookup the data-sheets, and read each section referred,
// 6.3.11, 8.4.1, 8.4.7 // 6.3.11, 8.4.1, 8.4.7
...@@ -102,12 +106,25 @@ fn main() -> ! { ...@@ -102,12 +106,25 @@ fn main() -> ! {
// What was the error message and explain why. // What was the error message and explain why.
// //
// ** your answer here ** // ** your answer here **
// error[E0133]: call to unsafe function is unsafe and requires unsafe function or block
// --> examples/bare4.rs:40:5
// |
// 40 | core::ptr::read_volatile(addr as *const _)
// | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ call to unsafe function
// |
// = note: consult the function's documentation for information on how to avoid undefined behavior
//
// error: aborting due to previous error
//
// read_voliatile is a unsafe so it panics
// //
// Digging a bit deeper, why do you think `read_volatile` is declared `unsafe`. // Digging a bit deeper, why do you think `read_volatile` is declared `unsafe`.
// (https://doc.rust-lang.org/core/ptr/fn.read_volatile.html, for some food for thought ) // (https://doc.rust-lang.org/core/ptr/fn.read_volatile.html, for some food for thought )
// //
// ** your answer here ** // ** your answer here **
// //
// because rust cant guarantee to know whats on the memmory address
//
// Commit your answers (bare4_2) // Commit your answers (bare4_2)
// //
// 3. Volatile read/writes are explicit *volatile operations* in Rust, while in C they // 3. Volatile read/writes are explicit *volatile operations* in Rust, while in C they
...@@ -121,14 +138,30 @@ fn main() -> ! { ...@@ -121,14 +138,30 @@ fn main() -> ! {
// //
// ** your answer here ** // ** your answer here **
// //
// because volatile just reads the momory address so if it is done in the wrong order it
// might read values that are wrong and the use them.
//
// Give an example in the above code, where reordering might make things go horribly wrong // Give an example in the above code, where reordering might make things go horribly wrong
// (hint, accessing a peripheral not being powered...) // (hint, accessing a peripheral not being powered...)
// //
// ** your answer here ** // ** your answer here **
// //
// // power on GPIOA
// let r = read_u32(RCC_AHB1ENR); // read
// write_u32(RCC_AHB1ENR, r | 1); // set enable
//
// //configure PA5 as output
// let r = read_u32(GPIOA_MODER) & !(0b11 << (5 * 2)); // read and mask
// write_u32(GPIOA_MODER, r | 0b01 << (5 * 2)); // set output mode
//
// if poweron giopa would happen after the config it could cause problems
//
// Without the non-reordering property of `write_volatile/read_volatile` could that happen in theory // Without the non-reordering property of `write_volatile/read_volatile` could that happen in theory
// (argue from the point of data dependencies). // (argue from the point of data dependencies).
// //
// ** your answer here ** // ** your answer here **
// //
// its important that they are non-reordering because otherwise if a write_volitile is dependent on data from a read_volitile
// and its reorderd it would not have all the relevent data it needs.
//
// Commit your answers (bare4_3) // Commit your answers (bare4_3)
examples/bare5.rs
View file @ 19008d4f
...@@ -9,16 +9,18 @@ ...@@ -9,16 +9,18 @@
#![no_std] #![no_std]
#![no_main] #![no_main]
extern crate panic_halt; extern crate panic_semihosting;
extern crate cortex_m; extern crate cortex_m;
use cortex_m_rt::entry; use cortex_m_rt::entry;
use cortex_m_semihosting::{hprint, hprintln};
// C like API... // C like API...
mod stm32f40x { mod stm32f40x {
#[allow(dead_code)] #[allow(dead_code)]
use core::{cell, ptr}; use core::{cell, ptr};
use cortex_m_semihosting::{hprint, hprintln};
#[rustfmt::skip] #[rustfmt::skip]
mod address { mod address {
pub const PERIPH_BASE: u32 = 0x40000000; pub const PERIPH_BASE: u32 = 0x40000000;
...@@ -51,18 +53,30 @@ mod stm32f40x { ...@@ -51,18 +53,30 @@ mod stm32f40x {
} }
//modify (reads, modifies a field, and writes the volatile cell) //modify (reads, modifies a field, and writes the volatile cell)
//
//parameters: //parameters:
//offset (field offset) //offset (field offset)
//width (field width) //width (field width)
//value (new value that the field should take) //value (new value that the field should take)
//
// impl VolatileCell<u32> { impl VolatileCell<u32> {
// #[inline(always)] #[inline(always)]
// pub fn modify(&self, offset: u8, width: u8, value: u32) { pub fn modify(&self, offset: u8, width: u8, value: u32) {
// // your code here unsafe{
// } let mut mask: u32 = 1;
// } for i in 0..width{
mask = mask | 1 << i;
}
mask = mask << offset;
let vaoff = (value << offset);
let vaoffmask = vaoff & mask;
let readinvmask = self.read() & !mask;
let finalval = readinvmask |vaoffmask;
hprintln!("{:#b}",finalval);
self.write(finalval);
}
}
}
#[repr(C)] #[repr(C)]
#[allow(non_snake_case)] #[allow(non_snake_case)]
...@@ -141,27 +155,28 @@ fn wait(i: u32) { ...@@ -141,27 +155,28 @@ fn wait(i: u32) {
} }
//simple test of Your `modify` //simple test of Your `modify`
//fn test() { fn test() {
// let t:VolatileCell<u32> = unsafe { core::mem::uninitialized() }; let t:VolatileCell<u32> = unsafe { core::mem::uninitialized() };
// t.write(0); t.write(0);
// assert!(t.read() == 0); assert!(t.read() == 0);
// t.modify(3, 3, 0b10101); hprintln!("{:?}", 123).unwrap();
// // t.modify(3, 3, 0b10101);
// // 10101 //
// // ..0111000 // 10101
// // --------- // ..0111000
// // 000101000 // ---------
// assert!(t.read() == 0b101 << 3); // 000101000
// t.modify(4, 3, 0b10001); assert!(t.read() == 0b101 << 3);
// // 000101000 t.modify(4, 3, 0b10001);
// // 111 // 000101000
// // 001 // 111
// // 000011000 // 001
// assert!(t.read() == 0b011 << 3); // 000011000
assert!(t.read() == 0b011 << 3);
//if << is used, your code will panic in dev (debug), but not in release mode //if << is used, your code will panic in dev (debug), but not in release mode
// t.modify(32, 3, 1); t.modify(32, 3, 1);
//} }
// system startup, can be hidden from the user // system startup, can be hidden from the user
#[entry] #[entry]
...@@ -169,7 +184,7 @@ fn main() -> ! { ...@@ -169,7 +184,7 @@ fn main() -> ! {
let rcc = unsafe { &mut *RCC::get() }; // get the reference to RCC in memory let rcc = unsafe { &mut *RCC::get() }; // get the reference to RCC in memory
let gpioa = unsafe { &mut *GPIOA::get() }; // get the reference to GPIOA in memory let gpioa = unsafe { &mut *GPIOA::get() }; // get the reference to GPIOA in memory
// test(); // uncomment to run test test(); // uncomment to run test
idle(rcc, gpioa); idle(rcc, gpioa);
loop { loop {
continue; continue;
...@@ -188,20 +203,20 @@ fn idle(rcc: &mut RCC, gpioa: &mut GPIOA) { ...@@ -188,20 +203,20 @@ fn idle(rcc: &mut RCC, gpioa: &mut GPIOA) {
loop { loop {
// set PA5 high // set PA5 high
gpioa.BSRRH.write(1 << 5); // set bit, output hight (turn on led) //gpioa.BSRRH.write(1 << 5); // set bit, output hight (turn on led)
// alternatively to set the bit high we can // alternatively to set the bit high we can
// read the value, or with PA5 (bit 5) and write back // read the value, or with PA5 (bit 5) and write back
// gpioa.ODR.write(gpioa.ODR.read() | (1 << 5)); gpioa.ODR.write(gpioa.ODR.read() | (1 << 5));
wait(10_000); wait(10_000);
// set PA5 low // set PA5 low
gpioa.BSRRL.write(1 << 5); // clear bit, output low (turn off led) //gpioa.BSRRL.write(1 << 5); // clear bit, output low (turn off led)
// alternatively to clear the bit we can // alternatively to clear the bit we can
// read the value, mask out PA5 (bit 5) and write back // read the value, mask out PA5 (bit 5) and write back
// gpioa.ODR.write(gpioa.ODR.read() & !(1 << 5)); gpioa.ODR.write(gpioa.ODR.read() & !(1 << 5));
wait(10_000); wait(10_000);
} }
} }
......
examples/bare8.rs
View file @ 19008d4f
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
extern crate panic_halt; extern crate panic_halt;
use cortex_m::iprintln; use cortex_m_semihosting::hprintln;
use nb::block; use nb::block;
extern crate stm32f4xx_hal as hal; extern crate stm32f4xx_hal as hal;
...@@ -30,7 +30,6 @@ const APP: () = { ...@@ -30,7 +30,6 @@ const APP: () = {
// Late resources // Late resources
TX: Tx<USART2>, TX: Tx<USART2>,
RX: Rx<USART2>, RX: Rx<USART2>,
ITM: ITM,
} }
// init runs in an interrupt free section // init runs in an interrupt free section
...@@ -39,8 +38,7 @@ const APP: () = { ...@@ -39,8 +38,7 @@ const APP: () = {
let mut core = cx.core; let mut core = cx.core;
let device = cx.device; let device = cx.device;
let stim = &mut core.ITM.stim[0]; hprintln!("bare8");
iprintln!(stim, "bare8");
let rcc = device.RCC.constrain(); let rcc = device.RCC.constrain();
...@@ -55,7 +53,7 @@ const APP: () = { ...@@ -55,7 +53,7 @@ const APP: () = {
let serial = Serial::usart2( let serial = Serial::usart2(
device.USART2, device.USART2,
(tx, rx), (tx, rx),
Config::default().baudrate(115_200.bps()), Config::default().baudrate(9_600.bps()),
clocks, clocks,
) )
.unwrap(); .unwrap();
...@@ -67,25 +65,23 @@ const APP: () = { ...@@ -67,25 +65,23 @@ const APP: () = {
init::LateResources { init::LateResources {
TX: tx, TX: tx,
RX: rx, RX: rx,
ITM: core.ITM,
} }
} }
// idle may be interrupted by other interrupts/tasks in the system // idle may be interrupted by other interrupts/tasks in the system
#[idle(resources = [RX, TX, ITM])] #[idle(resources = [RX, TX])]
fn idle(cx: idle::Context) -> ! { fn idle(cx: idle::Context) -> ! {
let rx = cx.resources.RX; let rx = cx.resources.RX;
let tx = cx.resources.TX; let tx = cx.resources.TX;
let stim = &mut cx.resources.ITM.stim[0];
loop { loop {
match block!(rx.read()) { match block!(rx.read()) {
Ok(byte) => { Ok(byte) => {
iprintln!(stim, "Ok {:?}", byte); hprintln!("Ok {:?}", byte);
tx.write(byte).unwrap(); tx.write(byte).unwrap();
} }
Err(err) => { Err(err) => {
iprintln!(stim, "Error {:?}", err); hprintln!("Error {:?}", err);
} }
} }
} }
......
examples/serial.rs
View file @ 19008d4f
...@@ -8,7 +8,6 @@ ...@@ -8,7 +8,6 @@
//! buffer may overflow. //! buffer may overflow.
#![deny(unsafe_code)] #![deny(unsafe_code)]
#![deny(warnings)]
#![no_main] #![no_main]
#![no_std] #![no_std]
...@@ -20,12 +19,11 @@ extern crate stm32f4xx_hal as hal; ...@@ -20,12 +19,11 @@ extern crate stm32f4xx_hal as hal;
use crate::hal::prelude::*; use crate::hal::prelude::*;
use crate::hal::serial::{config::Config, Serial}; use crate::hal::serial::{config::Config, Serial};
use cortex_m::iprintln; use cortex_m_semihosting::hprintln;
#[entry] #[entry]
fn main() -> ! { fn main() -> ! {
let mut c = hal::stm32::CorePeripherals::take().unwrap(); let mut c = hal::stm32::CorePeripherals::take().unwrap();
let stim = &mut c.ITM.stim[0]; //let stim = &mut c.ITM.stim[0];
let p = hal::stm32::Peripherals::take().unwrap(); let p = hal::stm32::Peripherals::take().unwrap();
...@@ -51,13 +49,13 @@ fn main() -> ! { ...@@ -51,13 +49,13 @@ fn main() -> ! {
let (mut tx, mut rx) = serial.split(); let (mut tx, mut rx) = serial.split();
loop { loop {
match block!(rx.read()) { match rx.read() {
Ok(byte) => { Ok(byte) => {
iprintln!(stim, "Ok {:?}", byte); hprintln!("Ok {:?}", byte).unwrap();
let _ = tx.write(byte); let _ = tx.write(byte);
} }
Err(err) => { Err(err) => {
iprintln!(stim, "Error {:?}", err); hprintln!( "Error {:?}", err).unwrap();
} }
} }
} }
......
openocd.cfg
View file @ 19008d4f
source [find interface/stlink.cfg] #source [find interface/stlink.cfg]
# deprecated # deprecated
# source [find interface/stlink-v2-1.cfg] source [find interface/stlink-v2-1.cfg]
transport select hla_swd transport select hla_swd
# increase working area to 64KB # increase working area to 64KB
......