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Anton Johansson
e7020e_2021
Commits
20ea1d20
Commit
20ea1d20
authored
4 years ago
by
Anton
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oscilloscope things
parent
73095e2f
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1 changed file
examples/rtic_bare6.rs
+26
-25
26 additions, 25 deletions
examples/rtic_bare6.rs
with
26 additions
and
25 deletions
examples/rtic_bare6.rs
+
26
−
25
View file @
20ea1d20
...
...
@@ -18,7 +18,8 @@ use stm32f4xx_hal::{
stm32
::{
self
,
GPIOC
,
RCC
},
};
const
OFFSET
:
u32
=
24_000_000
;
//const OFFSET: u32 = 24_000_000;
const
OFFSET
:
u32
=
8_000_000
;
#[rtic::app(device
=
stm32f4xx_hal::stm32,
monotonic
=
rtic::cyccnt::CYCCNT,
peripherals
=
true
)]
const
APP
:
()
=
{
...
...
@@ -58,11 +59,11 @@ const APP: () = {
// let _clocks = rcc.cfgr.freeze();
// Set up the system clock. 48 MHz?
let
_clocks
=
rcc
.cfgr
.sysclk
(
48
.mhz
())
.pclk1
(
24
.mhz
())
.freeze
();
//
let _clocks = rcc
//
.cfgr
//
.sysclk(48.mhz())
//
.pclk1(24.mhz())
//
.freeze();
// let _clocks = rcc
// .cfgr
...
...
@@ -71,12 +72,12 @@ const APP: () = {
// .pclk2(64.mhz())
// .freeze();
//
//
let _clocks = rcc
//
.cfgr
//
.sysclk(84.mhz())
//
.pclk1(42.mhz())
//
.pclk2(64.mhz())
//
.freeze();
let
_clocks
=
rcc
.cfgr
.sysclk
(
84
.mhz
())
.pclk1
(
42
.mhz
())
.pclk2
(
64
.mhz
())
.freeze
();
// pass on late resources
init
::
LateResources
{
...
...
@@ -138,7 +139,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
// otyper reset state push/pull, in reset state (don't need to change)
// ospeedr 0b11 = very high speed
gpioc
.ospeedr
.modify
(|
_
,
w
|
w
.ospeedr9
()
.
very_high
_speed
());
gpioc
.ospeedr
.modify
(|
_
,
w
|
w
.ospeedr9
()
.
low
_speed
());
}
// 0. Background reading:
...
...
@@ -207,7 +208,7 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// `rcc.cfgr.sysclk(84.mhz()).pclk1(42.mhz()).pclk2(64.mhz()).freeze();`
//
//
** your answer here **
//
Nothing?
//
// Start `stm32cubemx` and select or create a project targeting stm32f401.
// Go to the graphical clock configuration view.
...
...
@@ -255,11 +256,11 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// Compute the value of SYSCLK based on the oscilloscope reading
//
//
** your answer here **
//
about 4MHz
//
// What is the peak to peak (voltage) reading of the signal?
//
//
** your answer here **
//
between 4.7 - 4.8, alternating between them
//
// Make a folder called "pictures" in your git project.
// Make a screen dump or photo of the oscilloscope output.
...
...
@@ -283,15 +284,15 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// What is the frequency of MCO2 read by the oscilloscope?
//
//
** your answer here **
//
about 12 MHz
//
// Compute the value of SYSCLK based on the oscilloscope reading.
//
//
** your answer here **
//
about 48 MHz
//
// What is the peak to peak reading of the signal?
//
//
** your answer here **
//
4.9V
//
// Make a screen dump or photo of the oscilloscope output.
// Save the the picture as "bare_6_48mhz_high_speed".
...
...
@@ -326,11 +327,11 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// Did the frequency change in comparison to assignment 5?
//
//
** your answer here **
//
No it did not.
//
// What is the peak to peak reading of the signal (and why did it change)?
//
//
** your answer here **
//
about 3.6V.
//
// Make a screen dump or photo of the oscilloscope output.
// Save the the picture as "bare_6_48mhz_low_speed".
...
...
@@ -343,11 +344,11 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// Does the code compile?
//
//
** your answer here **
//
It does compile.
//
// What happens at run-time?
//
//
** your answer here **
//
Panik!!!!
//
// Try setting the clocks according to:
//
...
...
@@ -355,11 +356,11 @@ fn clock_out(rcc: &RCC, gpioc: &GPIOC) {
//
// Does the code compile?
//
//
** your answer here **
//
It work
//
// What happens at run-time?
//
//
** your answer here **
//
It work
//
// Is that a correct?
//
...
...
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