Handling NSS (Slave select) in hardware would be faster and easier.
The NSS pin is handled in software like a standard digital GPIO pin.
An undocumented hardware bug in the STMF7-series processor causes the hardware-managed NSS to malfunction if NSS Pulse was disabled.\cite{web:stm_nss_problem}
Handling NSS (Slave select) in hardware would be faster and easier, however an undocumented hardware bug in the STMF7-series processor causes the hardware-managed NSS to malfunction when NSS Pulse is disabled \cite{web:stm_nss_problem}.
An example of NSS Pulse mode can be seen in Figure \ref{pic:NSSP}.
An example of NSS Pulse mode can be seen in Figure \ref{pic:NSSP}.
The DW1000 does not support NSS Pulse communication, so software NSS was required.
The DW1000 does not support NSS Pulse communication, so software NSS was required.
The NSS pin is instead handled like a standard digital GPIO pin.
All other SPI is implemented using the HAL\footnote{Hardware Abstraction Layer} libraries supplied by STMicroelectronics for this processor.
All other SPI is implemented using the HAL\footnote{Hardware Abstraction Layer} libraries supplied by STMicroelectronics for this processor.
\begin{figure}[H]
\begin{figure}[H]
...
@@ -212,7 +211,7 @@
...
@@ -212,7 +211,7 @@
At maximum precision (\SI{0.25}{\degree} resolution and 3 byte per point) a total of $\frac{\SI{270}{\degree}}{0.25}=1080$ data points, resulting in 3240 bytes of data.
At maximum precision (\SI{0.25}{\degree} resolution and 3 byte per point) a total of $\frac{\SI{270}{\degree}}{0.25}=1080$ data points, resulting in 3240 bytes of data.