From d1f77301bd25589a24bf8c23d8deec9614840c50 Mon Sep 17 00:00:00 2001
From: sheepwall <a.sve@live.se>
Date: Wed, 13 Mar 2019 17:06:58 +0100
Subject: [PATCH] ..
---
examples/bare7.rs | 6 ++++--
openocd.gdb | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/examples/bare7.rs b/examples/bare7.rs
index 60675f5..bde535f 100644
--- a/examples/bare7.rs
+++ b/examples/bare7.rs
@@ -215,11 +215,13 @@ fn main() -> ! {
//
// What did you receive, and what was the output of the ITM trace.
//
-// ** your answer here **
+// ** Serial: abcd
+// ITM: Ok 97 Ok 98 Ok 99 Ok 100 **
//
// Explain why the buffer overflows.
//
-// ** your answer here **
+// ** There was no buffer overflow. I wrote 496 bytes, it failed after 336 ITM outputs.
+// It failed to echo after 425 characters. **
//
// commit your answers (bare7_4)
//
diff --git a/openocd.gdb b/openocd.gdb
index 376f825..fa49131 100644
--- a/openocd.gdb
+++ b/openocd.gdb
@@ -16,7 +16,7 @@ monitor arm semihosting enable
# send captured ITM to the file (fifo) /tmp/itm.log
# (the microcontroller SWO pin must be connected to the programmer SWO pin)
# 16000000 must match the core clock frequency
-monitor tpiu config internal /tmp/itm.log uart off 16000000 # 64000000
+monitor tpiu config internal /tmp/itm.log uart off 84000000 # 16000000 # 64000000
# OR: make the microcontroller SWO pin output compatible with UART (8N1)
# 8000000 must match the core clock frequency
--
GitLab