From b750c18ea90ba3183df8b2dd6645786317d2ba02 Mon Sep 17 00:00:00 2001
From: sheepwall <a.sve@live.se>
Date: Fri, 15 Mar 2019 09:49:46 +0100
Subject: [PATCH] bare8_1
---
examples/bare8.rs | 2 +-
openocd.gdb | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/examples/bare8.rs b/examples/bare8.rs
index b889d6c..6fec301 100644
--- a/examples/bare8.rs
+++ b/examples/bare8.rs
@@ -114,7 +114,7 @@ const APP: () = {
//
// 1. Our CPU now runs slower, did it effect the behavior?
//
-// ** your answer here **
+// ** Upon entering "aaaa", only "aa" is returned. **
//
// Commit your answer (bare8_1)
//
diff --git a/openocd.gdb b/openocd.gdb
index fa49131..a6d9e2a 100644
--- a/openocd.gdb
+++ b/openocd.gdb
@@ -16,7 +16,7 @@ monitor arm semihosting enable
# send captured ITM to the file (fifo) /tmp/itm.log
# (the microcontroller SWO pin must be connected to the programmer SWO pin)
# 16000000 must match the core clock frequency
-monitor tpiu config internal /tmp/itm.log uart off 84000000 # 16000000 # 64000000
+monitor tpiu config internal /tmp/itm.log uart off 16000000 # 84000000 # 64000000
# OR: make the microcontroller SWO pin output compatible with UART (8N1)
# 8000000 must match the core clock frequency
--
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