diff --git a/examples/bare8.rs b/examples/bare8.rs
index b889d6c41671797308d5359078bf4141eb1d7230..6fec30149a0100a58ed1aad33157f7f4ef16fbfa 100644
--- a/examples/bare8.rs
+++ b/examples/bare8.rs
@@ -114,7 +114,7 @@ const APP: () = {
 //
 // 1. Our CPU now runs slower, did it effect the behavior?
 //
-//    ** your answer here **
+//    ** Upon entering "aaaa", only "aa" is returned. **
 //
 //    Commit your answer (bare8_1)
 //
diff --git a/openocd.gdb b/openocd.gdb
index fa4913172c8c19c19ecbe4b70dec2917275973b5..a6d9e2a0d7327f54c0ad18d8d3d807716b381f38 100644
--- a/openocd.gdb
+++ b/openocd.gdb
@@ -16,7 +16,7 @@ monitor arm semihosting enable
 # send captured ITM to the file (fifo) /tmp/itm.log
 # (the microcontroller SWO pin must be connected to the programmer SWO pin)
 # 16000000 must match the core clock frequency
-monitor tpiu config internal /tmp/itm.log uart off 84000000 # 16000000 # 64000000
+monitor tpiu config internal /tmp/itm.log uart off 16000000 # 84000000 # 64000000
 
 # OR: make the microcontroller SWO pin output compatible with UART (8N1)
 # 8000000 must match the core clock frequency