diff --git a/examples/bare7.rs b/examples/bare7.rs index 5793e31e623d2d567965e3c0acbe39ef5e4ab363..60675f5c4c77ce74ce7d55c65a5a0d533b314879 100644 --- a/examples/bare7.rs +++ b/examples/bare7.rs @@ -34,7 +34,7 @@ fn main() -> ! { let rcc = p.RCC; // Output MCO2 to PC9 as SYSCLK/4: - rcc.cfgr.modify(|_, w| w.mco2().sysclk().mco2pre().div4()); + rcc.cfgr.modify(|_, w| w.mco2().sysclk().mco2pre().div1()); // Enable GPIOC: rcc.ahb1enr.modify(|_, w| w.gpiocen().enabled()); @@ -42,7 +42,7 @@ fn main() -> ! { // Set Port C pin 9 to alternate function MCO2. gpioc.moder.modify(|_, w| w.moder9().alternate()); - gpioc.ospeedr.modify(|_, w| w.ospeedr9().very_high_speed()); + gpioc.ospeedr.modify(|_, w| w.ospeedr9().low_speed()); // Now lock the clocks: let rcc = rcc.constrain(); @@ -175,17 +175,21 @@ fn main() -> ! { // // 3. Now reprogram the PC9 to be "Low Speed", and re-run at 84Mz. // -// Did the frequency change in comparison to assignment 5? +// Did the frequency change in comparison to assignment 5? << Assuming last task // -// ** your answer here ** +// ** The frequency is the same. BUT, changing the divider from 4 to 1, meaning +// that MCO2 = SYSCLK = 84 MHz, the output is zero, while it is not zero with +// "very_high_speed()" on. ** // // What is the peak to peak reading of the signal (and why did it change)? // -// ** your answer here ** +// ** Zero at MCO2 = 84 MHz and low_speed mode. 3.95 V at MCO = 21 MHz. ** // // Make a screen dump or photo of the oscilloscope output. // Save the the picture as "bare_6_84mhz_low_speed". // +// ** It is the MCO2 = 84 MHz, low_speed mode I put in the pictures/ folder. ** +// // Commit your answers (bare7_3) // // 4. Revisit the `README.md` regarding serial communication. diff --git a/pictures/bare_6_84mhz_low_speed.bmp b/pictures/bare_6_84mhz_low_speed.bmp new file mode 100644 index 0000000000000000000000000000000000000000..9f47a2dcd733b9cf7267a3f85a3833b9eaaa5b40 Binary files /dev/null and b/pictures/bare_6_84mhz_low_speed.bmp differ