diff --git a/examples/rtt_timing.rs b/examples/rtt_timing.rs
index 4ac047af7b4a891627992ff0d8f58cf75369d3fe..55ec24759e8368da6c8aa7cd01c962874ead1b0b 100644
--- a/examples/rtt_timing.rs
+++ b/examples/rtt_timing.rs
@@ -212,6 +212,22 @@ fn timed_loop() -> (u32, u32) {
 // (gdb) info registers
 //
 // [Register dump here]
+// r0             0x80000000       -2147483648
+// r1             0xe0001004       -536866812
+// r2             0x3e8    1000
+// r3             0xa      10
+// r4             0x20000000       536870912
+// r5             0x20000430       536871984
+// r6             0x0      0
+// r7             0x2000ffe8       536936424
+// r8             0x0      0
+// r9             0x0      0
+// r10            0x0      0
+// r11            0x0      0
+// r12            0x1      1
+// sp             0x2000ff98       0x2000ff98
+// lr             0x8000373        134218611
+// pc             0x800023e        0x800023e <rtt_timing::timed_loop+12>
 //
 // We can now set a breakpoint exactly at the `nop`.
 //
@@ -236,18 +252,18 @@ fn timed_loop() -> (u32, u32) {
 //
 // (gdb) x 0xe0001004
 //
-// [Your answer here]
+// [ 0xb0ccc188 ]
 //
 // Now, let's execute one iteration:
 // (gdb) continue
 //
 // What is now the current value of the cycle counter?
 //
-// [Your answer here]
+// [ 0xb0ccc18c ]
 //
 // By how much does the cycle counter increase for each iteration?
 //
-// [Your answer here]
+// [0xb0ccc18c - 0xb0ccc188 = 0x4]
 //
 // ------------------------------------------------------------------------
 // F) Reseting the cycle counter