Commit ad9a3dac authored by Per's avatar Per

14.0

parent b54e84d8
Pipeline #83 failed with stage
[package]
authors = ["Per Lindgren <per.lindgren@ltu.se>"]
description = "Peripheral access API for STM32F413/F423 microcontrollers"
documentation = "https://docs.rs/stm32f40x"
keywords = ["no-std", "arm", "cortex-m", "stm32"]
license = "MIT OR Apache-2.0"
name = "stm32f413"
version = "0.2.0"
version = "0.3.0"
[dependencies]
cortex-m = "0.4.0"
bare-metal = "0.1.1"
cortex-m = "0.5.8"
bare-metal = "0.2.4"
vcell = "0.1.0"
[dependencies.cortex-m-rt]
optional = true
version = "0.3.0"
version = "0.6.5"
[features]
rt = ["cortex-m-rt"]
\ No newline at end of file
use std::env;
use std::fs::File;
use std::io::Write;
use std::path::PathBuf;
fn main() {
if env::var_os("CARGO_FEATURE_RT").is_some() {
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
File::create(out.join("device.x"))
.unwrap()
.write_all(include_bytes!("device.x"))
.unwrap();
println!("cargo:rustc-link-search={}", out.display());
println!("cargo:rerun-if-changed=device.x");
}
println!("cargo:rerun-if-changed=build.rs");
}
PROVIDE(WWDG = DefaultHandler);
PROVIDE(PVD = DefaultHandler);
PROVIDE(TAMP_STAMP = DefaultHandler);
PROVIDE(RTC_WKUP = DefaultHandler);
PROVIDE(FLASH = DefaultHandler);
PROVIDE(RCC = DefaultHandler);
PROVIDE(EXTI0 = DefaultHandler);
PROVIDE(EXTI1 = DefaultHandler);
PROVIDE(EXTI2 = DefaultHandler);
PROVIDE(EXTI3 = DefaultHandler);
PROVIDE(EXTI4 = DefaultHandler);
PROVIDE(DMA1_STREAM0 = DefaultHandler);
PROVIDE(DMA1_STREAM1 = DefaultHandler);
PROVIDE(DMA1_STREAM2 = DefaultHandler);
PROVIDE(DMA1_STREAM3 = DefaultHandler);
PROVIDE(DMA1_STREAM4 = DefaultHandler);
PROVIDE(DMA1_STREAM5 = DefaultHandler);
PROVIDE(DMA1_STREAM6 = DefaultHandler);
PROVIDE(ADC = DefaultHandler);
PROVIDE(CAN1_TX = DefaultHandler);
PROVIDE(CAN1_RX0 = DefaultHandler);
PROVIDE(CAN1_RX1 = DefaultHandler);
PROVIDE(CAN1_SCE = DefaultHandler);
PROVIDE(EXTI9_5 = DefaultHandler);
PROVIDE(TIM1_BRK_TIM9 = DefaultHandler);
PROVIDE(TIM1_UP_TIM10 = DefaultHandler);
PROVIDE(TIM1_TRG_COM_TIM11 = DefaultHandler);
PROVIDE(TIM1_CC = DefaultHandler);
PROVIDE(TIM2 = DefaultHandler);
PROVIDE(TIM3 = DefaultHandler);
PROVIDE(TIM4 = DefaultHandler);
PROVIDE(I2C1_EVT = DefaultHandler);
PROVIDE(I2C1_ERR = DefaultHandler);
PROVIDE(I2C2_EVT = DefaultHandler);
PROVIDE(I2C2_ERR = DefaultHandler);
PROVIDE(SPI1 = DefaultHandler);
PROVIDE(SPI2 = DefaultHandler);
PROVIDE(USART1 = DefaultHandler);
PROVIDE(USART2 = DefaultHandler);
PROVIDE(USART3 = DefaultHandler);
PROVIDE(EXTI15_10 = DefaultHandler);
PROVIDE(EXTI17_RTC_ALARM = DefaultHandler);
PROVIDE(EXTI18_OTG_FS_WKUP = DefaultHandler);
PROVIDE(TIM8_BRK_TIM12 = DefaultHandler);
PROVIDE(TIM8_UP_TIM13 = DefaultHandler);
PROVIDE(TIM8_TRG_COM_TIM14 = DefaultHandler);
PROVIDE(TIM8_CC = DefaultHandler);
PROVIDE(DMA1_STREAM7 = DefaultHandler);
PROVIDE(FSMC = DefaultHandler);
PROVIDE(SDIO = DefaultHandler);
PROVIDE(TIM5 = DefaultHandler);
PROVIDE(SPI3 = DefaultHandler);
PROVIDE(USART4 = DefaultHandler);
PROVIDE(UART5 = DefaultHandler);
PROVIDE(TIM6_GLB_IT_DAC1_DAC2 = DefaultHandler);
PROVIDE(TIM7 = DefaultHandler);
PROVIDE(DMA2_STREAM0 = DefaultHandler);
PROVIDE(DMA2_STREAM1 = DefaultHandler);
PROVIDE(DMA2_STREAM2 = DefaultHandler);
PROVIDE(DMA2_STREAM3 = DefaultHandler);
PROVIDE(DMA2_STREAM4 = DefaultHandler);
PROVIDE(DFSDM1_FLT0 = DefaultHandler);
PROVIDE(DFSDM1_FLT1 = DefaultHandler);
PROVIDE(CAN2_TX = DefaultHandler);
PROVIDE(CAN2_RX0 = DefaultHandler);
PROVIDE(CAN2_RX1 = DefaultHandler);
PROVIDE(CAN2_SCE = DefaultHandler);
PROVIDE(OTG_FS_USB = DefaultHandler);
PROVIDE(DMA2_STREAM5 = DefaultHandler);
PROVIDE(DMA2_STREAM6 = DefaultHandler);
PROVIDE(DMA2_STREAM7 = DefaultHandler);
PROVIDE(USART6 = DefaultHandler);
PROVIDE(I2C3_EV = DefaultHandler);
PROVIDE(I2C3_ER = DefaultHandler);
PROVIDE(CAN3_TX = DefaultHandler);
PROVIDE(CAN3_RX0 = DefaultHandler);
PROVIDE(CAN3_RX1 = DefaultHandler);
PROVIDE(CAN3_SCE = DefaultHandler);
PROVIDE(CRYPTO = DefaultHandler);
PROVIDE(RNG = DefaultHandler);
PROVIDE(FPU = DefaultHandler);
PROVIDE(USART7 = DefaultHandler);
PROVIDE(USART8 = DefaultHandler);
PROVIDE(SPI4 = DefaultHandler);
PROVIDE(SPI5 = DefaultHandler);
PROVIDE(SAI1 = DefaultHandler);
PROVIDE(UART9 = DefaultHandler);
PROVIDE(UART10 = DefaultHandler);
PROVIDE(QUADSPI = DefaultHandler);
PROVIDE(I2CFMP1EVENT = DefaultHandler);
PROVIDE(I2CFMP1ERROR = DefaultHandler);
PROVIDE(LPTIM1_OR_IT_EIT_23 = DefaultHandler);
PROVIDE(DFSDM2_FILTER1 = DefaultHandler);
PROVIDE(DFSDM2_FILTER2 = DefaultHandler);
PROVIDE(DFSDM2_FILTER3 = DefaultHandler);
PROVIDE(DFSDM2_FILTER4 = DefaultHandler);
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct ADCPRER {
bits: u8,
}
impl ADCPRER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct VBATER {
bits: bool,
}
impl VBATER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct TSVREFER {
bits: bool,
}
impl TSVREFER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Proxy"]
pub struct _ADCPREW<'a> {
w: &'a mut W,
}
impl<'a> _ADCPREW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _VBATEW<'a> {
w: &'a mut W,
}
impl<'a> _VBATEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TSVREFEW<'a> {
w: &'a mut W,
}
impl<'a> _TSVREFEW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 16:17 - ADC prescaler"]
#[inline]
pub fn adcpre(&self) -> ADCPRER {
let bits = {
const MASK: u8 = 3;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
ADCPRER { bits }
}
#[doc = "Bit 22 - VBAT enable"]
#[inline]
pub fn vbate(&self) -> VBATER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
};
VBATER { bits }
}
#[doc = "Bit 23 - Temperature sensor and VREFINT enable"]
#[inline]
pub fn tsvrefe(&self) -> TSVREFER {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
};
TSVREFER { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 16:17 - ADC prescaler"]
#[inline]
pub fn adcpre(&mut self) -> _ADCPREW {
_ADCPREW { w: self }
}
#[doc = "Bit 22 - VBAT enable"]
#[inline]
pub fn vbate(&mut self) -> _VBATEW {
_VBATEW { w: self }
}
#[doc = "Bit 23 - Temperature sensor and VREFINT enable"]
#[inline]
pub fn tsvrefe(&mut self) -> _TSVREFEW {
_TSVREFEW { w: self }
}
}
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