diff --git a/src/lib.rs b/src/lib.rs
index c41571d1cc6cc05386abaa443e91c5de1bd558ea..5d77f6aac32b8a11b915c293eff333a61994a7e8 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -8,7 +8,7 @@ extern crate vcell;
use core::ops::Deref;
use bare_metal::Peripheral;
#[doc = r" Number available in the NVIC for configuring priority"]
-pub const NVIC_PRIO_BITS: u8 = 3;
+pub const NVIC_PRIO_BITS: u8 = 4;
pub use interrupt::Interrupt;
#[doc(hidden)]
pub mod interrupt {
@@ -241,105 +241,7 @@ pub mod interrupt {
Some(DFSDM2_FILTER4),
];
#[doc = r" Enumeration of all the interrupts"]
- pub enum Interrupt {
- #[doc = "0 - Window Watchdog interrupt"] WWDG,
- #[doc = "1 - PVD through EXTI line detection interrupt"] PVD,
- #[doc = "2 - Tamper and TimeStamp interrupts through the EXTI line"] TAMP_STAMP,
- #[doc = "3 - RTC Wakeup interrupt through the EXTI line"] RTC_WKUP,
- #[doc = "4 - FLASH global interrupt"] FLASH,
- #[doc = "5 - RCC global interrupt"] RCC,
- #[doc = "6 - EXTI Line0 interrupt"] EXTI0,
- #[doc = "7 - EXTI Line1 interrupt"] EXTI1,
- #[doc = "8 - EXTI Line2 interrupt"] EXTI2,
- #[doc = "9 - EXTI Line3 interrupt"] EXTI3,
- #[doc = "10 - EXTI Line4 interrupt"] EXTI4,
- #[doc = "11 - DMA1 Stream0 global interrupt"] DMA1_STREAM0,
- #[doc = "12 - DMA1 Stream1 global interrupt"] DMA1_STREAM1,
- #[doc = "13 - DMA1 Stream2 global interrupt"] DMA1_STREAM2,
- #[doc = "14 - DMA1 Stream3 global interrupt"] DMA1_STREAM3,
- #[doc = "15 - DMA1 Stream4 global interrupt"] DMA1_STREAM4,
- #[doc = "16 - DMA1 Stream5 global interrupt"] DMA1_STREAM5,
- #[doc = "17 - DMA1 Stream6 global interrupt"] DMA1_STREAM6,
- #[doc = "18 - ADC1 global interrupt"] ADC,
- #[doc = "19 - CAN1 TX interrupts"] CAN1_TX,
- #[doc = "20 - CAN1 RX0 interrupts"] CAN1_RX0,
- #[doc = "21 - CAN1 RX1 interrupts"] CAN1_RX1,
- #[doc = "22 - CAN1 SCE interrupt"] CAN1_SCE,
- #[doc = "23 - EXTI Line[9:5] interrupts"] EXTI9_5,
- #[doc = "24 - TIM1 Break interrupt and TIM9 global interrupt"] TIM1_BRK_TIM9,
- #[doc = "25 - TIM1 Update interrupt and TIM10 global interrupt"] TIM1_UP_TIM10,
- #[doc = "26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt"]
- TIM1_TRG_COM_TIM11,
- #[doc = "27 - TIM1 Capture Compare interrupt"] TIM1_CC,
- #[doc = "28 - TIM2 global interrupt"] TIM2,
- #[doc = "29 - TIM3 global interrupt"] TIM3,
- #[doc = "30 - TIM4 global interrupt"] TIM4,
- #[doc = "31 - I2C1 event interrupt"] I2C1_EVT,
- #[doc = "32 - I2C1 error interrupt"] I2C1_ERR,
- #[doc = "33 - I2C2 event interrupt"] I2C2_EVT,
- #[doc = "34 - I2C2 error interrupt"] I2C2_ERR,
- #[doc = "35 - SPI1 global interrupt"] SPI1,
- #[doc = "36 - SPI2 global interrupt"] SPI2,
- #[doc = "37 - USART1 global interrupt"] USART1,
- #[doc = "38 - USART2 global interrupt"] USART2,
- #[doc = "39 - USART3 global interrupt"] USART3,
- #[doc = "40 - EXTI Line[15:10] interrupts"] EXTI15_10,
- #[doc = "41 - RTC Alarms (A and B) through EXTI line interrupt"] EXTI17_RTC_ALARM,
- #[doc = "42 - USB On-The-Go FS Wakeup through EXTI line interrupt"] EXTI18_OTG_FS_WKUP,
- #[doc = "43 - Timer 12 global interrupt"] TIM8_BRK_TIM12,
- #[doc = "44 - Timer 13 global interrupt"] TIM8_UP_TIM13,
- #[doc = "45 - Timer 14 global interrupt"] TIM8_TRG_COM_TIM14,
- #[doc = "46 - TIM8 Cap/Com interrupt"] TIM8_CC,
- #[doc = "47 - DMA1 global interrupt Channel 7"] DMA1_STREAM7,
- #[doc = "48 - FSMC global interrupt"] FSMC,
- #[doc = "49 - SDIO global interrupt"] SDIO,
- #[doc = "50 - TIM5 global interrupt"] TIM5,
- #[doc = "51 - SPI3 global interrupt"] SPI3,
- #[doc = "52 - UART 4 global interrupt"] USART4,
- #[doc = "53 - UART 5global interrupt"] UART5,
- #[doc = "54 - TIM6 global and DAC12 underrun interrupts"] TIM6_GLB_IT_DAC1_DAC2,
- #[doc = "55 - TIM7 global interrupt"] TIM7,
- #[doc = "56 - DMA2 Stream0 global interrupt"] DMA2_STREAM0,
- #[doc = "57 - DMA2 Stream1 global interrupt"] DMA2_STREAM1,
- #[doc = "58 - DMA2 Stream2 global interrupt"] DMA2_STREAM2,
- #[doc = "59 - DMA2 Stream3 global interrupt"] DMA2_STREAM3,
- #[doc = "60 - DMA2 Stream4 global interrupt"] DMA2_STREAM4,
- #[doc = "61 - SD filter0 global interrupt"] DFSDM1_FLT0,
- #[doc = "62 - SD filter1 global interrupt"] DFSDM1_FLT1,
- #[doc = "63 - CAN2 TX interrupt"] CAN2_TX,
- #[doc = "64 - BXCAN2 RX0 interrupt"] CAN2_RX0,
- #[doc = "65 - BXCAN2 RX1 interrupt"] CAN2_RX1,
- #[doc = "66 - CAN2 SCE interrupt"] CAN2_SCE,
- #[doc = "67 - USB On The Go FS global interrupt"] OTG_FS_USB,
- #[doc = "68 - DMA2 Stream5 global interrupt"] DMA2_STREAM5,
- #[doc = "69 - DMA2 Stream6 global interrupt"] DMA2_STREAM6,
- #[doc = "70 - DMA2 Stream7 global interrupt"] DMA2_STREAM7,
- #[doc = "71 - USART6 global interrupt"] USART6,
- #[doc = "72 - I2C3 event interrupt"] I2C3_EV,
- #[doc = "73 - I2C3 error interrupt"] I2C3_ER,
- #[doc = "74 - CAN 3 TX interrupt"] CAN3_TX,
- #[doc = "75 - BxCAN 3 RX0 interrupt"] CAN3_RX0,
- #[doc = "76 - BxCAN 3 RX1 interrupt"] CAN3_RX1,
- #[doc = "77 - CAN 3 SCE interrupt"] CAN3_SCE,
- #[doc = "79 - AES global interrupt"] CRYPTO,
- #[doc = "80 - Rng global interrupt"] RNG,
- #[doc = "81 - FPU global interrupt"] FPU,
- #[doc = "82 - USART7 global interrupt"] USART7,
- #[doc = "83 - USART8 global interrupt"] USART8,
- #[doc = "84 - SPI4 global interrupt"] SPI4,
- #[doc = "85 - SPI5 global interrupt"] SPI5,
- #[doc = "87 - SAI1 global interrupt"] SAI1,
- #[doc = "88 - UART9 global interrupt"] UART9,
- #[doc = "89 - UART10 global interrupt"] UART10,
- #[doc = "92 - Quad-SPI global interrupt"] QUADSPI,
- #[doc = "95 - I2CFMP1 event interrupt"] I2CFMP1EVENT,
- #[doc = "96 - I2CFMP1 error interrupt"] I2CFMP1ERROR,
- #[doc = "97 - LP Timer global interrupt or EXT1 interrupt line 23"] LPTIM1_OR_IT_EIT_23,
- #[doc = "98 - DFSDM2 SD filter 1 global interrupt"] DFSDM2_FILTER1,
- #[doc = "99 - DFSDM2 SD filter 2 global interrupt"] DFSDM2_FILTER2,
- #[doc = "100 - DFSDM2 SD filter 3 global interrupt"] DFSDM2_FILTER3,
- #[doc = "101 - DFSDM2 SD filter 4 global interrupt"] DFSDM2_FILTER4,
- }
+ pub enum Interrupt {# [ doc = "0 - Window Watchdog interrupt" ] WWDG , # [ doc = "1 - PVD through EXTI line detection interrupt" ] PVD , # [ doc = "2 - Tamper and TimeStamp interrupts through the EXTI line" ] TAMP_STAMP , # [ doc = "3 - RTC Wakeup interrupt through the EXTI line" ] RTC_WKUP , # [ doc = "4 - FLASH global interrupt" ] FLASH , # [ doc = "5 - RCC global interrupt" ] RCC , # [ doc = "6 - EXTI Line0 interrupt" ] EXTI0 , # [ doc = "7 - EXTI Line1 interrupt" ] EXTI1 , # [ doc = "8 - EXTI Line2 interrupt" ] EXTI2 , # [ doc = "9 - EXTI Line3 interrupt" ] EXTI3 , # [ doc = "10 - EXTI Line4 interrupt" ] EXTI4 , # [ doc = "11 - DMA1 Stream0 global interrupt" ] DMA1_STREAM0 , # [ doc = "12 - DMA1 Stream1 global interrupt" ] DMA1_STREAM1 , # [ doc = "13 - DMA1 Stream2 global interrupt" ] DMA1_STREAM2 , # [ doc = "14 - DMA1 Stream3 global interrupt" ] DMA1_STREAM3 , # [ doc = "15 - DMA1 Stream4 global interrupt" ] DMA1_STREAM4 , # [ doc = "16 - DMA1 Stream5 global interrupt" ] DMA1_STREAM5 , # [ doc = "17 - DMA1 Stream6 global interrupt" ] DMA1_STREAM6 , # [ doc = "18 - ADC1 global interrupt" ] ADC , # [ doc = "19 - CAN1 TX interrupts" ] CAN1_TX , # [ doc = "20 - CAN1 RX0 interrupts" ] CAN1_RX0 , # [ doc = "21 - CAN1 RX1 interrupts" ] CAN1_RX1 , # [ doc = "22 - CAN1 SCE interrupt" ] CAN1_SCE , # [ doc = "23 - EXTI Line[9:5] interrupts" ] EXTI9_5 , # [ doc = "24 - TIM1 Break interrupt and TIM9 global interrupt" ] TIM1_BRK_TIM9 , # [ doc = "25 - TIM1 Update interrupt and TIM10 global interrupt" ] TIM1_UP_TIM10 , # [ doc = "26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt" ] TIM1_TRG_COM_TIM11 , # [ doc = "27 - TIM1 Capture Compare interrupt" ] TIM1_CC , # [ doc = "28 - TIM2 global interrupt" ] TIM2 , # [ doc = "29 - TIM3 global interrupt" ] TIM3 , # [ doc = "30 - TIM4 global interrupt" ] TIM4 , # [ doc = "31 - I2C1 event interrupt" ] I2C1_EVT , # [ doc = "32 - I2C1 error interrupt" ] I2C1_ERR , # [ doc = "33 - I2C2 event interrupt" ] I2C2_EVT , # [ doc = "34 - I2C2 error interrupt" ] I2C2_ERR , # [ doc = "35 - SPI1 global interrupt" ] SPI1 , # [ doc = "36 - SPI2 global interrupt" ] SPI2 , # [ doc = "37 - USART1 global interrupt" ] USART1 , # [ doc = "38 - USART2 global interrupt" ] USART2 , # [ doc = "39 - USART3 global interrupt" ] USART3 , # [ doc = "40 - EXTI Line[15:10] interrupts" ] EXTI15_10 , # [ doc = "41 - RTC Alarms (A and B) through EXTI line interrupt" ] EXTI17_RTC_ALARM , # [ doc = "42 - USB On-The-Go FS Wakeup through EXTI line interrupt" ] EXTI18_OTG_FS_WKUP , # [ doc = "43 - Timer 12 global interrupt" ] TIM8_BRK_TIM12 , # [ doc = "44 - Timer 13 global interrupt" ] TIM8_UP_TIM13 , # [ doc = "45 - Timer 14 global interrupt" ] TIM8_TRG_COM_TIM14 , # [ doc = "46 - TIM8 Cap/Com interrupt" ] TIM8_CC , # [ doc = "47 - DMA1 global interrupt Channel 7" ] DMA1_STREAM7 , # [ doc = "48 - FSMC global interrupt" ] FSMC , # [ doc = "49 - SDIO global interrupt" ] SDIO , # [ doc = "50 - TIM5 global interrupt" ] TIM5 , # [ doc = "51 - SPI3 global interrupt" ] SPI3 , # [ doc = "52 - UART 4 global interrupt" ] USART4 , # [ doc = "53 - UART 5global interrupt" ] UART5 , # [ doc = "54 - TIM6 global and DAC12 underrun interrupts" ] TIM6_GLB_IT_DAC1_DAC2 , # [ doc = "55 - TIM7 global interrupt" ] TIM7 , # [ doc = "56 - DMA2 Stream0 global interrupt" ] DMA2_STREAM0 , # [ doc = "57 - DMA2 Stream1 global interrupt" ] DMA2_STREAM1 , # [ doc = "58 - DMA2 Stream2 global interrupt" ] DMA2_STREAM2 , # [ doc = "59 - DMA2 Stream3 global interrupt" ] DMA2_STREAM3 , # [ doc = "60 - DMA2 Stream4 global interrupt" ] DMA2_STREAM4 , # [ doc = "61 - SD filter0 global interrupt" ] DFSDM1_FLT0 , # [ doc = "62 - SD filter1 global interrupt" ] DFSDM1_FLT1 , # [ doc = "63 - CAN2 TX interrupt" ] CAN2_TX , # [ doc = "64 - BXCAN2 RX0 interrupt" ] CAN2_RX0 , # [ doc = "65 - BXCAN2 RX1 interrupt" ] CAN2_RX1 , # [ doc = "66 - CAN2 SCE interrupt" ] CAN2_SCE , # [ doc = "67 - USB On The Go FS global interrupt" ] OTG_FS_USB , # [ doc = "68 - DMA2 Stream5 global interrupt" ] DMA2_STREAM5 , # [ doc = "69 - DMA2 Stream6 global interrupt" ] DMA2_STREAM6 , # [ doc = "70 - DMA2 Stream7 global interrupt" ] DMA2_STREAM7 , # [ doc = "71 - USART6 global interrupt" ] USART6 , # [ doc = "72 - I2C3 event interrupt" ] I2C3_EV , # [ doc = "73 - I2C3 error interrupt" ] I2C3_ER , # [ doc = "74 - CAN 3 TX interrupt" ] CAN3_TX , # [ doc = "75 - BxCAN 3 RX0 interrupt" ] CAN3_RX0 , # [ doc = "76 - BxCAN 3 RX1 interrupt" ] CAN3_RX1 , # [ doc = "77 - CAN 3 SCE interrupt" ] CAN3_SCE , # [ doc = "79 - AES global interrupt" ] CRYPTO , # [ doc = "80 - Rng global interrupt" ] RNG , # [ doc = "81 - FPU global interrupt" ] FPU , # [ doc = "82 - USART7 global interrupt" ] USART7 , # [ doc = "83 - USART8 global interrupt" ] USART8 , # [ doc = "84 - SPI4 global interrupt" ] SPI4 , # [ doc = "85 - SPI5 global interrupt" ] SPI5 , # [ doc = "87 - SAI1 global interrupt" ] SAI1 , # [ doc = "88 - UART9 global interrupt" ] UART9 , # [ doc = "89 - UART10 global interrupt" ] UART10 , # [ doc = "92 - Quad-SPI global interrupt" ] QUADSPI , # [ doc = "95 - I2CFMP1 event interrupt" ] I2CFMP1EVENT , # [ doc = "96 - I2CFMP1 error interrupt" ] I2CFMP1ERROR , # [ doc = "97 - LP Timer global interrupt or EXT1 interrupt line 23" ] LPTIM1_OR_IT_EIT_23 , # [ doc = "98 - DFSDM2 SD filter 1 global interrupt" ] DFSDM2_FILTER1 , # [ doc = "99 - DFSDM2 SD filter 2 global interrupt" ] DFSDM2_FILTER2 , # [ doc = "100 - DFSDM2 SD filter 3 global interrupt" ] DFSDM2_FILTER3 , # [ doc = "101 - DFSDM2 SD filter 4 global interrupt" ] DFSDM2_FILTER4 ,}
unsafe impl Nr for Interrupt {
#[inline(always)]
fn nr(&self) -> u8 {
@@ -1635,8 +1537,7 @@ pub mod adc1 {
};
JAUTOR { bits }
}
- #[doc = "Bit 9 - Enable the watchdog on a single channel in scan mode"]
- #[inline(always)]
+ # [ doc = "Bit 9 - Enable the watchdog on a single channel in scan mode" ] # [ inline ( always ) ]
pub fn awdsgl(&self) -> AWDSGLR {
let bits = {
const MASK: bool = true;
@@ -1748,8 +1649,7 @@ pub mod adc1 {
pub fn jauto(&mut self) -> _JAUTOW {
_JAUTOW { w: self }
}
- #[doc = "Bit 9 - Enable the watchdog on a single channel in scan mode"]
- #[inline(always)]
+ # [ doc = "Bit 9 - Enable the watchdog on a single channel in scan mode" ] # [ inline ( always ) ]
pub fn awdsgl(&mut self) -> _AWDSGLW {
_AWDSGLW { w: self }
}
@@ -6869,12 +6769,16 @@ pub mod dbg {
}
#[doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"]
#[inline(always)]
- pub fn dbg_i2c1_smbus_timeout(&mut self) -> _DBG_I2C1_SMBUS_TIMEOUTW {
+ pub fn dbg_i2c1_smbus_timeout(
+ &mut self,
+ ) -> _DBG_I2C1_SMBUS_TIMEOUTW {
_DBG_I2C1_SMBUS_TIMEOUTW { w: self }
}
#[doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"]
#[inline(always)]
- pub fn dbg_i2c2_smbus_timeout(&mut self) -> _DBG_I2C2_SMBUS_TIMEOUTW {
+ pub fn dbg_i2c2_smbus_timeout(
+ &mut self,
+ ) -> _DBG_I2C2_SMBUS_TIMEOUTW {
_DBG_I2C2_SMBUS_TIMEOUTW { w: self }
}
#[doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"]
@@ -19200,8 +19104,7 @@ pub mod pwr {
};
BRER { bits }
}
- #[doc = "Bit 14 - Regulator voltage scaling output selection ready bit"]
- #[inline(always)]
+ # [ doc = "Bit 14 - Regulator voltage scaling output selection ready bit" ] # [ inline ( always ) ]
pub fn vosrdy(&self) -> VOSRDYR {
let bits = {
const MASK: bool = true;
@@ -19233,8 +19136,7 @@ pub mod pwr {
pub fn bre(&mut self) -> _BREW {
_BREW { w: self }
}
- #[doc = "Bit 14 - Regulator voltage scaling output selection ready bit"]
- #[inline(always)]
+ # [ doc = "Bit 14 - Regulator voltage scaling output selection ready bit" ] # [ inline ( always ) ]
pub fn vosrdy(&mut self) -> _VOSRDYW {
_VOSRDYW { w: self }
}
@@ -19258,68 +19160,7 @@ pub mod rcc {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - clock control register"]
- pub cr: CR,
- #[doc = "0x04 - PLL configuration register"]
- pub pllcfgr: PLLCFGR,
- #[doc = "0x08 - clock configuration register"]
- pub cfgr: CFGR,
- #[doc = "0x0c - clock interrupt register"]
- pub cir: CIR,
- #[doc = "0x10 - AHB1 peripheral reset register"]
- pub ahb1rstr: AHB1RSTR,
- #[doc = "0x14 - AHB2 peripheral reset register"]
- pub ahb2rstr: AHB2RSTR,
- #[doc = "0x18 - peripheral reset register"]
- pub ahb3rstr: AHB3RSTR,
- _reserved0: [u8; 4usize],
- #[doc = "0x20 - APB1 peripheral reset register"]
- pub apb1rstr: APB1RSTR,
- #[doc = "0x24 - APB2 peripheral reset register"]
- pub apb2rstr: APB2RSTR,
- _reserved1: [u8; 8usize],
- #[doc = "0x30 - AHB1 peripheral clock register"]
- pub ahb1enr: AHB1ENR,
- #[doc = "0x34 - AHB2 peripheral clock enable register"]
- pub ahb2enr: AHB2ENR,
- #[doc = "0x38 - AHB3 peripheral clock enable register"]
- pub ahb3enr: AHB3ENR,
- _reserved2: [u8; 4usize],
- #[doc = "0x40 - APB1 peripheral clock enable register"]
- pub apb1enr: APB1ENR,
- #[doc = "0x44 - APB2 peripheral clock enable register"]
- pub apb2enr: APB2ENR,
- _reserved3: [u8; 8usize],
- #[doc = "0x50 - AHB1 peripheral clock enable in low power mode register"]
- pub ahb1lpenr: AHB1LPENR,
- #[doc = "0x54 - AHB2 peripheral clock enable in low power mode register"]
- pub ahb2lpenr: AHB2LPENR,
- #[doc = "0x58 - AHB3 peripheral clock enable in low power mode register"]
- pub ahb3lpenr: AHB3LPENR,
- _reserved4: [u8; 4usize],
- #[doc = "0x60 - APB1 peripheral clock enable in low power mode register"]
- pub apb1lpenr: APB1LPENR,
- #[doc = "0x64 - APB2 peripheral clock enabled in low power mode register"]
- pub apb2lpenr: APB2LPENR,
- _reserved5: [u8; 8usize],
- #[doc = "0x70 - Backup domain control register"]
- pub bdcr: BDCR,
- #[doc = "0x74 - clock control & status register"]
- pub csr: CSR,
- _reserved6: [u8; 8usize],
- #[doc = "0x80 - spread spectrum clock generation register"]
- pub sscgr: SSCGR,
- #[doc = "0x84 - PLLI2S configuration register"]
- pub plli2scfgr: PLLI2SCFGR,
- _reserved7: [u8; 4usize],
- #[doc = "0x8c - Dedicated Clocks Configuration Register"]
- pub dckcfgr: DCKCFGR,
- #[doc = "0x90 - RCC clocks gated enable register"]
- pub ckgatenr: CKGATENR,
- #[doc = "0x94 - Dedicated Clocks Configuration Register"]
- pub dckcfgr2: DCKCFGR2,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - clock control register" ] pub cr : CR , # [ doc = "0x04 - PLL configuration register" ] pub pllcfgr : PLLCFGR , # [ doc = "0x08 - clock configuration register" ] pub cfgr : CFGR , # [ doc = "0x0c - clock interrupt register" ] pub cir : CIR , # [ doc = "0x10 - AHB1 peripheral reset register" ] pub ahb1rstr : AHB1RSTR , # [ doc = "0x14 - AHB2 peripheral reset register" ] pub ahb2rstr : AHB2RSTR , # [ doc = "0x18 - peripheral reset register" ] pub ahb3rstr : AHB3RSTR , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x20 - APB1 peripheral reset register" ] pub apb1rstr : APB1RSTR , # [ doc = "0x24 - APB2 peripheral reset register" ] pub apb2rstr : APB2RSTR , _reserved1 : [ u8 ; 8usize ] , # [ doc = "0x30 - AHB1 peripheral clock register" ] pub ahb1enr : AHB1ENR , # [ doc = "0x34 - AHB2 peripheral clock enable register" ] pub ahb2enr : AHB2ENR , # [ doc = "0x38 - AHB3 peripheral clock enable register" ] pub ahb3enr : AHB3ENR , _reserved2 : [ u8 ; 4usize ] , # [ doc = "0x40 - APB1 peripheral clock enable register" ] pub apb1enr : APB1ENR , # [ doc = "0x44 - APB2 peripheral clock enable register" ] pub apb2enr : APB2ENR , _reserved3 : [ u8 ; 8usize ] , # [ doc = "0x50 - AHB1 peripheral clock enable in low power mode register" ] pub ahb1lpenr : AHB1LPENR , # [ doc = "0x54 - AHB2 peripheral clock enable in low power mode register" ] pub ahb2lpenr : AHB2LPENR , # [ doc = "0x58 - AHB3 peripheral clock enable in low power mode register" ] pub ahb3lpenr : AHB3LPENR , _reserved4 : [ u8 ; 4usize ] , # [ doc = "0x60 - APB1 peripheral clock enable in low power mode register" ] pub apb1lpenr : APB1LPENR , # [ doc = "0x64 - APB2 peripheral clock enabled in low power mode register" ] pub apb2lpenr : APB2LPENR , _reserved5 : [ u8 ; 8usize ] , # [ doc = "0x70 - Backup domain control register" ] pub bdcr : BDCR , # [ doc = "0x74 - clock control & status register" ] pub csr : CSR , _reserved6 : [ u8 ; 8usize ] , # [ doc = "0x80 - spread spectrum clock generation register" ] pub sscgr : SSCGR , # [ doc = "0x84 - PLLI2S configuration register" ] pub plli2scfgr : PLLI2SCFGR , _reserved7 : [ u8 ; 4usize ] , # [ doc = "0x8c - Dedicated Clocks Configuration Register" ] pub dckcfgr : DCKCFGR , # [ doc = "0x90 - RCC clocks gated enable register" ] pub ckgatenr : CKGATENR , # [ doc = "0x94 - Dedicated Clocks Configuration Register" ] pub dckcfgr2 : DCKCFGR2 , }
#[doc = "clock control register"]
pub struct CR {
register: VolatileCell<u32>,
@@ -21149,8 +20990,7 @@ pub mod rcc {
};
PLLQ0R { bits }
}
- #[doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"]
- #[inline(always)]
+ # [ doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source" ] # [ inline ( always ) ]
pub fn pllsrc(&self) -> PLLSRCR {
let bits = {
const MASK: bool = true;
@@ -21159,8 +20999,7 @@ pub mod rcc {
};
PLLSRCR { bits }
}
- #[doc = "Bit 17 - Main PLL (PLL) division factor for main system clock"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Main PLL (PLL) division factor for main system clock" ] # [ inline ( always ) ]
pub fn pllp1(&self) -> PLLP1R {
let bits = {
const MASK: bool = true;
@@ -21169,8 +21008,7 @@ pub mod rcc {
};
PLLP1R { bits }
}
- #[doc = "Bit 16 - Main PLL (PLL) division factor for main system clock"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Main PLL (PLL) division factor for main system clock" ] # [ inline ( always ) ]
pub fn pllp0(&self) -> PLLP0R {
let bits = {
const MASK: bool = true;
@@ -21323,8 +21161,7 @@ pub mod rcc {
};
PLLM0R { bits }
}
- #[doc = "Bits 28:30 - Main PLL (PLL) division factor for I2S, DFSDM clocks"]
- #[inline(always)]
+ # [ doc = "Bits 28:30 - Main PLL (PLL) division factor for I2S, DFSDM clocks" ] # [ inline ( always ) ]
pub fn pllr(&self) -> PLLRR {
let bits = {
const MASK: u8 = 7;
@@ -21362,18 +21199,15 @@ pub mod rcc {
pub fn pllq0(&mut self) -> _PLLQ0W {
_PLLQ0W { w: self }
}
- #[doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"]
- #[inline(always)]
+ # [ doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source" ] # [ inline ( always ) ]
pub fn pllsrc(&mut self) -> _PLLSRCW {
_PLLSRCW { w: self }
}
- #[doc = "Bit 17 - Main PLL (PLL) division factor for main system clock"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Main PLL (PLL) division factor for main system clock" ] # [ inline ( always ) ]
pub fn pllp1(&mut self) -> _PLLP1W {
_PLLP1W { w: self }
}
- #[doc = "Bit 16 - Main PLL (PLL) division factor for main system clock"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Main PLL (PLL) division factor for main system clock" ] # [ inline ( always ) ]
pub fn pllp0(&mut self) -> _PLLP0W {
_PLLP0W { w: self }
}
@@ -21446,8 +21280,7 @@ pub mod rcc {
pub fn pllm0(&mut self) -> _PLLM0W {
_PLLM0W { w: self }
}
- #[doc = "Bits 28:30 - Main PLL (PLL) division factor for I2S, DFSDM clocks"]
- #[inline(always)]
+ # [ doc = "Bits 28:30 - Main PLL (PLL) division factor for I2S, DFSDM clocks" ] # [ inline ( always ) ]
pub fn pllr(&mut self) -> _PLLRW {
_PLLRW { w: self }
}
@@ -31608,8 +31441,7 @@ pub mod rcc {
};
RNGLPENR { bits }
}
- #[doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn fsmclpen(&self) -> FSMCLPENR {
let bits = {
const MASK: bool = true;
@@ -31618,8 +31450,7 @@ pub mod rcc {
};
FSMCLPENR { bits }
}
- #[doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn qspilpen(&self) -> QSPILPENR {
let bits = {
const MASK: bool = true;
@@ -31651,13 +31482,11 @@ pub mod rcc {
pub fn rnglpen(&mut self) -> _RNGLPENW {
_RNGLPENW { w: self }
}
- #[doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn fsmclpen(&mut self) -> _FSMCLPENW {
_FSMCLPENW { w: self }
}
- #[doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn qspilpen(&mut self) -> _QSPILPENW {
_QSPILPENW { w: self }
}
@@ -34417,8 +34246,7 @@ pub mod rcc {
};
SPI4LPENR { bits }
}
- #[doc = "Bit 14 - System configuration controller clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 14 - System configuration controller clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn syscfglpen(&self) -> SYSCFGLPENR {
let bits = {
const MASK: bool = true;
@@ -34487,8 +34315,7 @@ pub mod rcc {
};
USART10LPENR { bits }
}
- #[doc = "Bit 15 - EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 15 - EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn extiten(&self) -> EXTITENR {
let bits = {
const MASK: bool = true;
@@ -34580,8 +34407,7 @@ pub mod rcc {
pub fn spi4lpen(&mut self) -> _SPI4LPENW {
_SPI4LPENW { w: self }
}
- #[doc = "Bit 14 - System configuration controller clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 14 - System configuration controller clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn syscfglpen(&mut self) -> _SYSCFGLPENW {
_SYSCFGLPENW { w: self }
}
@@ -34615,8 +34441,7 @@ pub mod rcc {
pub fn usart10lpen(&mut self) -> _USART10LPENW {
_USART10LPENW { w: self }
}
- #[doc = "Bit 15 - EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 15 - EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn extiten(&mut self) -> _EXTITENW {
_EXTITENW { w: self }
}
@@ -36299,8 +36124,7 @@ pub mod rcc {
};
PLLI2SSRCR { bits }
}
- #[doc = "Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock" ] # [ inline ( always ) ]
pub fn plli2sq(&self) -> PLLI2SQR {
let bits = {
const MASK: u8 = 15;
@@ -36341,8 +36165,7 @@ pub mod rcc {
pub fn plli2ssrc(&mut self) -> _PLLI2SSRCW {
_PLLI2SSRCW { w: self }
}
- #[doc = "Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock" ] # [ inline ( always ) ]
pub fn plli2sq(&mut self) -> _PLLI2SQW {
_PLLI2SQW { w: self }
}
@@ -36870,8 +36693,7 @@ pub mod rcc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn fsmclpen(&self) -> FSMCLPENR {
let bits = {
const MASK: bool = true;
@@ -36880,8 +36702,7 @@ pub mod rcc {
};
FSMCLPENR { bits }
}
- #[doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn qspilpen(&self) -> QSPILPENR {
let bits = {
const MASK: bool = true;
@@ -36903,13 +36724,11 @@ pub mod rcc {
self.bits = bits;
self
}
- #[doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn fsmclpen(&mut self) -> _FSMCLPENW {
_FSMCLPENW { w: self }
}
- #[doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode"]
- #[inline(always)]
+ # [ doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode" ] # [ inline ( always ) ]
pub fn qspilpen(&mut self) -> _QSPILPENW {
_QSPILPENW { w: self }
}
@@ -44675,8 +44494,7 @@ pub mod rtc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 24:27 - Mask the most-significant bits starting at this bit"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Mask the most-significant bits starting at this bit" ] # [ inline ( always ) ]
pub fn maskss(&self) -> MASKSSR {
let bits = {
const MASK: u8 = 15;
@@ -44708,8 +44526,7 @@ pub mod rtc {
self.bits = bits;
self
}
- #[doc = "Bits 24:27 - Mask the most-significant bits starting at this bit"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Mask the most-significant bits starting at this bit" ] # [ inline ( always ) ]
pub fn maskss(&mut self) -> _MASKSSW {
_MASKSSW { w: self }
}
@@ -44828,8 +44645,7 @@ pub mod rtc {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 24:27 - Mask the most-significant bits starting at this bit"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Mask the most-significant bits starting at this bit" ] # [ inline ( always ) ]
pub fn maskss(&self) -> MASKSSR {
let bits = {
const MASK: u8 = 15;
@@ -44861,8 +44677,7 @@ pub mod rtc {
self.bits = bits;
self
}
- #[doc = "Bits 24:27 - Mask the most-significant bits starting at this bit"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Mask the most-significant bits starting at this bit" ] # [ inline ( always ) ]
pub fn maskss(&mut self) -> _MASKSSW {
_MASKSSW { w: self }
}
@@ -48309,8 +48124,7 @@ pub mod sdio {
};
CPSMENR { bits }
}
- #[doc = "Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)." ] # [ inline ( always ) ]
pub fn waitpend(&self) -> WAITPENDR {
let bits = {
const MASK: bool = true;
@@ -48387,8 +48201,7 @@ pub mod sdio {
pub fn cpsmen(&mut self) -> _CPSMENW {
_CPSMENW { w: self }
}
- #[doc = "Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)."]
- #[inline(always)]
+ # [ doc = "Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)." ] # [ inline ( always ) ]
pub fn waitpend(&mut self) -> _WAITPENDW {
_WAITPENDW { w: self }
}
@@ -50032,8 +49845,7 @@ pub mod sdio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 23 - CE-ATA command completion signal received for CMD61"]
- #[inline(always)]
+ # [ doc = "Bit 23 - CE-ATA command completion signal received for CMD61" ] # [ inline ( always ) ]
pub fn ceataend(&self) -> CEATAENDR {
let bits = {
const MASK: bool = true;
@@ -50112,8 +49924,7 @@ pub mod sdio {
};
TXFIFOFR { bits }
}
- #[doc = "Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO"]
- #[inline(always)]
+ # [ doc = "Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO" ] # [ inline ( always ) ]
pub fn rxfifohf(&self) -> RXFIFOHFR {
let bits = {
const MASK: bool = true;
@@ -50171,8 +49982,7 @@ pub mod sdio {
};
DBCKENDR { bits }
}
- #[doc = "Bit 9 - Start bit not detected on all data signals in wide bus mode"]
- #[inline(always)]
+ # [ doc = "Bit 9 - Start bit not detected on all data signals in wide bus mode" ] # [ inline ( always ) ]
pub fn stbiterr(&self) -> STBITERRR {
let bits = {
const MASK: bool = true;
@@ -52223,8 +52033,7 @@ pub mod sdio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 23 - CE-ATA command completion signal received interrupt enable"]
- #[inline(always)]
+ # [ doc = "Bit 23 - CE-ATA command completion signal received interrupt enable" ] # [ inline ( always ) ]
pub fn ceataendie(&self) -> CEATAENDIER {
let bits = {
const MASK: bool = true;
@@ -52476,8 +52285,7 @@ pub mod sdio {
self.bits = bits;
self
}
- #[doc = "Bit 23 - CE-ATA command completion signal received interrupt enable"]
- #[inline(always)]
+ # [ doc = "Bit 23 - CE-ATA command completion signal received interrupt enable" ] # [ inline ( always ) ]
pub fn ceataendie(&mut self) -> _CEATAENDIEW {
_CEATAENDIEW { w: self }
}
@@ -52634,8 +52442,7 @@ pub mod sdio {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:23 - Remaining number of words to be written to or read from the FIFO."]
- #[inline(always)]
+ # [ doc = "Bits 0:23 - Remaining number of words to be written to or read from the FIFO." ] # [ inline ( always ) ]
pub fn fifocount(&self) -> FIFOCOUNTR {
let bits = {
const MASK: u32 = 16777215;
@@ -95079,8 +94886,7 @@ pub mod dma2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 27 - Stream x transfer complete interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 27 - Stream x transfer complete interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn tcif3(&self) -> TCIF3R {
let bits = {
const MASK: bool = true;
@@ -95109,8 +94915,7 @@ pub mod dma2 {
};
TEIF3R { bits }
}
- #[doc = "Bit 24 - Stream x direct mode error interrupt flag (x=3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 24 - Stream x direct mode error interrupt flag (x=3..0)" ] # [ inline ( always ) ]
pub fn dmeif3(&self) -> DMEIF3R {
let bits = {
const MASK: bool = true;
@@ -95129,8 +94934,7 @@ pub mod dma2 {
};
FEIF3R { bits }
}
- #[doc = "Bit 21 - Stream x transfer complete interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Stream x transfer complete interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn tcif2(&self) -> TCIF2R {
let bits = {
const MASK: bool = true;
@@ -95159,8 +94963,7 @@ pub mod dma2 {
};
TEIF2R { bits }
}
- #[doc = "Bit 18 - Stream x direct mode error interrupt flag (x=3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Stream x direct mode error interrupt flag (x=3..0)" ] # [ inline ( always ) ]
pub fn dmeif2(&self) -> DMEIF2R {
let bits = {
const MASK: bool = true;
@@ -95179,8 +94982,7 @@ pub mod dma2 {
};
FEIF2R { bits }
}
- #[doc = "Bit 11 - Stream x transfer complete interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 11 - Stream x transfer complete interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn tcif1(&self) -> TCIF1R {
let bits = {
const MASK: bool = true;
@@ -95229,8 +95031,7 @@ pub mod dma2 {
};
FEIF1R { bits }
}
- #[doc = "Bit 5 - Stream x transfer complete interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Stream x transfer complete interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn tcif0(&self) -> TCIF0R {
let bits = {
const MASK: bool = true;
@@ -95726,8 +95527,7 @@ pub mod dma2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 27 - Stream x transfer complete interrupt flag (x=7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 27 - Stream x transfer complete interrupt flag (x=7..4)" ] # [ inline ( always ) ]
pub fn tcif7(&self) -> TCIF7R {
let bits = {
const MASK: bool = true;
@@ -95756,8 +95556,7 @@ pub mod dma2 {
};
TEIF7R { bits }
}
- #[doc = "Bit 24 - Stream x direct mode error interrupt flag (x=7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 24 - Stream x direct mode error interrupt flag (x=7..4)" ] # [ inline ( always ) ]
pub fn dmeif7(&self) -> DMEIF7R {
let bits = {
const MASK: bool = true;
@@ -95776,8 +95575,7 @@ pub mod dma2 {
};
FEIF7R { bits }
}
- #[doc = "Bit 21 - Stream x transfer complete interrupt flag (x=7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Stream x transfer complete interrupt flag (x=7..4)" ] # [ inline ( always ) ]
pub fn tcif6(&self) -> TCIF6R {
let bits = {
const MASK: bool = true;
@@ -95806,8 +95604,7 @@ pub mod dma2 {
};
TEIF6R { bits }
}
- #[doc = "Bit 18 - Stream x direct mode error interrupt flag (x=7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Stream x direct mode error interrupt flag (x=7..4)" ] # [ inline ( always ) ]
pub fn dmeif6(&self) -> DMEIF6R {
let bits = {
const MASK: bool = true;
@@ -95826,8 +95623,7 @@ pub mod dma2 {
};
FEIF6R { bits }
}
- #[doc = "Bit 11 - Stream x transfer complete interrupt flag (x=7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 11 - Stream x transfer complete interrupt flag (x=7..4)" ] # [ inline ( always ) ]
pub fn tcif5(&self) -> TCIF5R {
let bits = {
const MASK: bool = true;
@@ -96422,103 +96218,83 @@ pub mod dma2 {
self.bits = bits;
self
}
- #[doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn ctcif3(&mut self) -> _CTCIF3W {
_CTCIF3W { w: self }
}
- #[doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn chtif3(&mut self) -> _CHTIF3W {
_CHTIF3W { w: self }
}
- #[doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cteif3(&mut self) -> _CTEIF3W {
_CTEIF3W { w: self }
}
- #[doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cdmeif3(&mut self) -> _CDMEIF3W {
_CDMEIF3W { w: self }
}
- #[doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cfeif3(&mut self) -> _CFEIF3W {
_CFEIF3W { w: self }
}
- #[doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn ctcif2(&mut self) -> _CTCIF2W {
_CTCIF2W { w: self }
}
- #[doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn chtif2(&mut self) -> _CHTIF2W {
_CHTIF2W { w: self }
}
- #[doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cteif2(&mut self) -> _CTEIF2W {
_CTEIF2W { w: self }
}
- #[doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cdmeif2(&mut self) -> _CDMEIF2W {
_CDMEIF2W { w: self }
}
- #[doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cfeif2(&mut self) -> _CFEIF2W {
_CFEIF2W { w: self }
}
- #[doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn ctcif1(&mut self) -> _CTCIF1W {
_CTCIF1W { w: self }
}
- #[doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn chtif1(&mut self) -> _CHTIF1W {
_CHTIF1W { w: self }
}
- #[doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cteif1(&mut self) -> _CTEIF1W {
_CTEIF1W { w: self }
}
- #[doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cdmeif1(&mut self) -> _CDMEIF1W {
_CDMEIF1W { w: self }
}
- #[doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cfeif1(&mut self) -> _CFEIF1W {
_CFEIF1W { w: self }
}
- #[doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn ctcif0(&mut self) -> _CTCIF0W {
_CTCIF0W { w: self }
}
- #[doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn chtif0(&mut self) -> _CHTIF0W {
_CHTIF0W { w: self }
}
- #[doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cteif0(&mut self) -> _CTEIF0W {
_CTEIF0W { w: self }
}
- #[doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cdmeif0(&mut self) -> _CDMEIF0W {
_CDMEIF0W { w: self }
}
- #[doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)" ] # [ inline ( always ) ]
pub fn cfeif0(&mut self) -> _CFEIF0W {
_CFEIF0W { w: self }
}
@@ -97018,103 +96794,83 @@ pub mod dma2 {
self.bits = bits;
self
}
- #[doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn ctcif7(&mut self) -> _CTCIF7W {
_CTCIF7W { w: self }
}
- #[doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn chtif7(&mut self) -> _CHTIF7W {
_CHTIF7W { w: self }
}
- #[doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cteif7(&mut self) -> _CTEIF7W {
_CTEIF7W { w: self }
}
- #[doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cdmeif7(&mut self) -> _CDMEIF7W {
_CDMEIF7W { w: self }
}
- #[doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cfeif7(&mut self) -> _CFEIF7W {
_CFEIF7W { w: self }
}
- #[doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn ctcif6(&mut self) -> _CTCIF6W {
_CTCIF6W { w: self }
}
- #[doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn chtif6(&mut self) -> _CHTIF6W {
_CHTIF6W { w: self }
}
- #[doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cteif6(&mut self) -> _CTEIF6W {
_CTEIF6W { w: self }
}
- #[doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cdmeif6(&mut self) -> _CDMEIF6W {
_CDMEIF6W { w: self }
}
- #[doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cfeif6(&mut self) -> _CFEIF6W {
_CFEIF6W { w: self }
}
- #[doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn ctcif5(&mut self) -> _CTCIF5W {
_CTCIF5W { w: self }
}
- #[doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn chtif5(&mut self) -> _CHTIF5W {
_CHTIF5W { w: self }
}
- #[doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cteif5(&mut self) -> _CTEIF5W {
_CTEIF5W { w: self }
}
- #[doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cdmeif5(&mut self) -> _CDMEIF5W {
_CDMEIF5W { w: self }
}
- #[doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cfeif5(&mut self) -> _CFEIF5W {
_CFEIF5W { w: self }
}
- #[doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn ctcif4(&mut self) -> _CTCIF4W {
_CTCIF4W { w: self }
}
- #[doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn chtif4(&mut self) -> _CHTIF4W {
_CHTIF4W { w: self }
}
- #[doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cteif4(&mut self) -> _CTEIF4W {
_CTEIF4W { w: self }
}
- #[doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cdmeif4(&mut self) -> _CDMEIF4W {
_CDMEIF4W { w: self }
}
- #[doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"]
- #[inline(always)]
+ # [ doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)" ] # [ inline ( always ) ]
pub fn cfeif4(&mut self) -> _CFEIF4W {
_CFEIF4W { w: self }
}
@@ -98604,8 +98360,7 @@ pub mod dma2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&self) -> M1AR {
let bits = {
const MASK: u32 = 4294967295;
@@ -98627,8 +98382,7 @@ pub mod dma2 {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&mut self) -> _M1AW {
_M1AW { w: self }
}
@@ -100428,8 +100182,7 @@ pub mod dma2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&self) -> M1AR {
let bits = {
const MASK: u32 = 4294967295;
@@ -100451,8 +100204,7 @@ pub mod dma2 {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&mut self) -> _M1AW {
_M1AW { w: self }
}
@@ -102252,8 +102004,7 @@ pub mod dma2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&self) -> M1AR {
let bits = {
const MASK: u32 = 4294967295;
@@ -102275,8 +102026,7 @@ pub mod dma2 {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&mut self) -> _M1AW {
_M1AW { w: self }
}
@@ -104076,8 +103826,7 @@ pub mod dma2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&self) -> M1AR {
let bits = {
const MASK: u32 = 4294967295;
@@ -104099,8 +103848,7 @@ pub mod dma2 {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&mut self) -> _M1AW {
_M1AW { w: self }
}
@@ -105900,8 +105648,7 @@ pub mod dma2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&self) -> M1AR {
let bits = {
const MASK: u32 = 4294967295;
@@ -105923,8 +105670,7 @@ pub mod dma2 {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&mut self) -> _M1AW {
_M1AW { w: self }
}
@@ -107724,8 +107470,7 @@ pub mod dma2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&self) -> M1AR {
let bits = {
const MASK: u32 = 4294967295;
@@ -107747,8 +107492,7 @@ pub mod dma2 {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&mut self) -> _M1AW {
_M1AW { w: self }
}
@@ -109548,8 +109292,7 @@ pub mod dma2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&self) -> M1AR {
let bits = {
const MASK: u32 = 4294967295;
@@ -109571,8 +109314,7 @@ pub mod dma2 {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&mut self) -> _M1AW {
_M1AW { w: self }
}
@@ -111372,8 +111114,7 @@ pub mod dma2 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&self) -> M1AR {
let bits = {
const MASK: u32 = 4294967295;
@@ -111395,8 +111136,7 @@ pub mod dma2 {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ( always ) ]
pub fn m1a(&mut self) -> _M1AW {
_M1AW { w: self }
}
@@ -118709,8 +118449,7 @@ pub mod gpioh {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl7(&self) -> AFRL7R {
let bits = {
const MASK: u8 = 15;
@@ -118719,8 +118458,7 @@ pub mod gpioh {
};
AFRL7R { bits }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl6(&self) -> AFRL6R {
let bits = {
const MASK: u8 = 15;
@@ -118729,8 +118467,7 @@ pub mod gpioh {
};
AFRL6R { bits }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl5(&self) -> AFRL5R {
let bits = {
const MASK: u8 = 15;
@@ -118739,8 +118476,7 @@ pub mod gpioh {
};
AFRL5R { bits }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl4(&self) -> AFRL4R {
let bits = {
const MASK: u8 = 15;
@@ -118749,8 +118485,7 @@ pub mod gpioh {
};
AFRL4R { bits }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl3(&self) -> AFRL3R {
let bits = {
const MASK: u8 = 15;
@@ -118759,8 +118494,7 @@ pub mod gpioh {
};
AFRL3R { bits }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl2(&self) -> AFRL2R {
let bits = {
const MASK: u8 = 15;
@@ -118769,8 +118503,7 @@ pub mod gpioh {
};
AFRL2R { bits }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl1(&self) -> AFRL1R {
let bits = {
const MASK: u8 = 15;
@@ -118779,8 +118512,7 @@ pub mod gpioh {
};
AFRL1R { bits }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl0(&self) -> AFRL0R {
let bits = {
const MASK: u8 = 15;
@@ -118802,43 +118534,35 @@ pub mod gpioh {
self.bits = bits;
self
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl7(&mut self) -> _AFRL7W {
_AFRL7W { w: self }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl6(&mut self) -> _AFRL6W {
_AFRL6W { w: self }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl5(&mut self) -> _AFRL5W {
_AFRL5W { w: self }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl4(&mut self) -> _AFRL4W {
_AFRL4W { w: self }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl3(&mut self) -> _AFRL3W {
_AFRL3W { w: self }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl2(&mut self) -> _AFRL2W {
_AFRL2W { w: self }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl1(&mut self) -> _AFRL1W {
_AFRL1W { w: self }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl0(&mut self) -> _AFRL0W {
_AFRL0W { w: self }
}
@@ -119108,8 +118832,7 @@ pub mod gpioh {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh15(&self) -> AFRH15R {
let bits = {
const MASK: u8 = 15;
@@ -119118,8 +118841,7 @@ pub mod gpioh {
};
AFRH15R { bits }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh14(&self) -> AFRH14R {
let bits = {
const MASK: u8 = 15;
@@ -119128,8 +118850,7 @@ pub mod gpioh {
};
AFRH14R { bits }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh13(&self) -> AFRH13R {
let bits = {
const MASK: u8 = 15;
@@ -119138,8 +118859,7 @@ pub mod gpioh {
};
AFRH13R { bits }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh12(&self) -> AFRH12R {
let bits = {
const MASK: u8 = 15;
@@ -119148,8 +118868,7 @@ pub mod gpioh {
};
AFRH12R { bits }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh11(&self) -> AFRH11R {
let bits = {
const MASK: u8 = 15;
@@ -119158,8 +118877,7 @@ pub mod gpioh {
};
AFRH11R { bits }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh10(&self) -> AFRH10R {
let bits = {
const MASK: u8 = 15;
@@ -119168,8 +118886,7 @@ pub mod gpioh {
};
AFRH10R { bits }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh9(&self) -> AFRH9R {
let bits = {
const MASK: u8 = 15;
@@ -119178,8 +118895,7 @@ pub mod gpioh {
};
AFRH9R { bits }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh8(&self) -> AFRH8R {
let bits = {
const MASK: u8 = 15;
@@ -119201,43 +118917,35 @@ pub mod gpioh {
self.bits = bits;
self
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh15(&mut self) -> _AFRH15W {
_AFRH15W { w: self }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh14(&mut self) -> _AFRH14W {
_AFRH14W { w: self }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh13(&mut self) -> _AFRH13W {
_AFRH13W { w: self }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh12(&mut self) -> _AFRH12W {
_AFRH12W { w: self }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh11(&mut self) -> _AFRH11W {
_AFRH11W { w: self }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh10(&mut self) -> _AFRH10W {
_AFRH10W { w: self }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh9(&mut self) -> _AFRH9W {
_AFRH9W { w: self }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh8(&mut self) -> _AFRH8W {
_AFRH8W { w: self }
}
@@ -126347,8 +126055,7 @@ pub mod gpiob {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl7(&self) -> AFRL7R {
let bits = {
const MASK: u8 = 15;
@@ -126357,8 +126064,7 @@ pub mod gpiob {
};
AFRL7R { bits }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl6(&self) -> AFRL6R {
let bits = {
const MASK: u8 = 15;
@@ -126367,8 +126073,7 @@ pub mod gpiob {
};
AFRL6R { bits }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl5(&self) -> AFRL5R {
let bits = {
const MASK: u8 = 15;
@@ -126377,8 +126082,7 @@ pub mod gpiob {
};
AFRL5R { bits }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl4(&self) -> AFRL4R {
let bits = {
const MASK: u8 = 15;
@@ -126387,8 +126091,7 @@ pub mod gpiob {
};
AFRL4R { bits }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl3(&self) -> AFRL3R {
let bits = {
const MASK: u8 = 15;
@@ -126397,8 +126100,7 @@ pub mod gpiob {
};
AFRL3R { bits }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl2(&self) -> AFRL2R {
let bits = {
const MASK: u8 = 15;
@@ -126407,8 +126109,7 @@ pub mod gpiob {
};
AFRL2R { bits }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl1(&self) -> AFRL1R {
let bits = {
const MASK: u8 = 15;
@@ -126417,8 +126118,7 @@ pub mod gpiob {
};
AFRL1R { bits }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl0(&self) -> AFRL0R {
let bits = {
const MASK: u8 = 15;
@@ -126440,43 +126140,35 @@ pub mod gpiob {
self.bits = bits;
self
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl7(&mut self) -> _AFRL7W {
_AFRL7W { w: self }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl6(&mut self) -> _AFRL6W {
_AFRL6W { w: self }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl5(&mut self) -> _AFRL5W {
_AFRL5W { w: self }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl4(&mut self) -> _AFRL4W {
_AFRL4W { w: self }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl3(&mut self) -> _AFRL3W {
_AFRL3W { w: self }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl2(&mut self) -> _AFRL2W {
_AFRL2W { w: self }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl1(&mut self) -> _AFRL1W {
_AFRL1W { w: self }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl0(&mut self) -> _AFRL0W {
_AFRL0W { w: self }
}
@@ -126746,8 +126438,7 @@ pub mod gpiob {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh15(&self) -> AFRH15R {
let bits = {
const MASK: u8 = 15;
@@ -126756,8 +126447,7 @@ pub mod gpiob {
};
AFRH15R { bits }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh14(&self) -> AFRH14R {
let bits = {
const MASK: u8 = 15;
@@ -126766,8 +126456,7 @@ pub mod gpiob {
};
AFRH14R { bits }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh13(&self) -> AFRH13R {
let bits = {
const MASK: u8 = 15;
@@ -126776,8 +126465,7 @@ pub mod gpiob {
};
AFRH13R { bits }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh12(&self) -> AFRH12R {
let bits = {
const MASK: u8 = 15;
@@ -126786,8 +126474,7 @@ pub mod gpiob {
};
AFRH12R { bits }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh11(&self) -> AFRH11R {
let bits = {
const MASK: u8 = 15;
@@ -126796,8 +126483,7 @@ pub mod gpiob {
};
AFRH11R { bits }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh10(&self) -> AFRH10R {
let bits = {
const MASK: u8 = 15;
@@ -126806,8 +126492,7 @@ pub mod gpiob {
};
AFRH10R { bits }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh9(&self) -> AFRH9R {
let bits = {
const MASK: u8 = 15;
@@ -126816,8 +126501,7 @@ pub mod gpiob {
};
AFRH9R { bits }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh8(&self) -> AFRH8R {
let bits = {
const MASK: u8 = 15;
@@ -126839,43 +126523,35 @@ pub mod gpiob {
self.bits = bits;
self
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh15(&mut self) -> _AFRH15W {
_AFRH15W { w: self }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh14(&mut self) -> _AFRH14W {
_AFRH14W { w: self }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh13(&mut self) -> _AFRH13W {
_AFRH13W { w: self }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh12(&mut self) -> _AFRH12W {
_AFRH12W { w: self }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh11(&mut self) -> _AFRH11W {
_AFRH11W { w: self }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh10(&mut self) -> _AFRH10W {
_AFRH10W { w: self }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh9(&mut self) -> _AFRH9W {
_AFRH9W { w: self }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh8(&mut self) -> _AFRH8W {
_AFRH8W { w: self }
}
@@ -133925,8 +133601,7 @@ pub mod gpioa {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl7(&self) -> AFRL7R {
let bits = {
const MASK: u8 = 15;
@@ -133935,8 +133610,7 @@ pub mod gpioa {
};
AFRL7R { bits }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl6(&self) -> AFRL6R {
let bits = {
const MASK: u8 = 15;
@@ -133945,8 +133619,7 @@ pub mod gpioa {
};
AFRL6R { bits }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl5(&self) -> AFRL5R {
let bits = {
const MASK: u8 = 15;
@@ -133955,8 +133628,7 @@ pub mod gpioa {
};
AFRL5R { bits }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl4(&self) -> AFRL4R {
let bits = {
const MASK: u8 = 15;
@@ -133965,8 +133637,7 @@ pub mod gpioa {
};
AFRL4R { bits }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl3(&self) -> AFRL3R {
let bits = {
const MASK: u8 = 15;
@@ -133975,8 +133646,7 @@ pub mod gpioa {
};
AFRL3R { bits }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl2(&self) -> AFRL2R {
let bits = {
const MASK: u8 = 15;
@@ -133985,8 +133655,7 @@ pub mod gpioa {
};
AFRL2R { bits }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl1(&self) -> AFRL1R {
let bits = {
const MASK: u8 = 15;
@@ -133995,8 +133664,7 @@ pub mod gpioa {
};
AFRL1R { bits }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl0(&self) -> AFRL0R {
let bits = {
const MASK: u8 = 15;
@@ -134018,43 +133686,35 @@ pub mod gpioa {
self.bits = bits;
self
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl7(&mut self) -> _AFRL7W {
_AFRL7W { w: self }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl6(&mut self) -> _AFRL6W {
_AFRL6W { w: self }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl5(&mut self) -> _AFRL5W {
_AFRL5W { w: self }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl4(&mut self) -> _AFRL4W {
_AFRL4W { w: self }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl3(&mut self) -> _AFRL3W {
_AFRL3W { w: self }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl2(&mut self) -> _AFRL2W {
_AFRL2W { w: self }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl1(&mut self) -> _AFRL1W {
_AFRL1W { w: self }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ( always ) ]
pub fn afrl0(&mut self) -> _AFRL0W {
_AFRL0W { w: self }
}
@@ -134324,8 +133984,7 @@ pub mod gpioa {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh15(&self) -> AFRH15R {
let bits = {
const MASK: u8 = 15;
@@ -134334,8 +133993,7 @@ pub mod gpioa {
};
AFRH15R { bits }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh14(&self) -> AFRH14R {
let bits = {
const MASK: u8 = 15;
@@ -134344,8 +134002,7 @@ pub mod gpioa {
};
AFRH14R { bits }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh13(&self) -> AFRH13R {
let bits = {
const MASK: u8 = 15;
@@ -134354,8 +134011,7 @@ pub mod gpioa {
};
AFRH13R { bits }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh12(&self) -> AFRH12R {
let bits = {
const MASK: u8 = 15;
@@ -134364,8 +134020,7 @@ pub mod gpioa {
};
AFRH12R { bits }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh11(&self) -> AFRH11R {
let bits = {
const MASK: u8 = 15;
@@ -134374,8 +134029,7 @@ pub mod gpioa {
};
AFRH11R { bits }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh10(&self) -> AFRH10R {
let bits = {
const MASK: u8 = 15;
@@ -134384,8 +134038,7 @@ pub mod gpioa {
};
AFRH10R { bits }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh9(&self) -> AFRH9R {
let bits = {
const MASK: u8 = 15;
@@ -134394,8 +134047,7 @@ pub mod gpioa {
};
AFRH9R { bits }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh8(&self) -> AFRH8R {
let bits = {
const MASK: u8 = 15;
@@ -134417,43 +134069,35 @@ pub mod gpioa {
self.bits = bits;
self
}
- #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh15(&mut self) -> _AFRH15W {
_AFRH15W { w: self }
}
- #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh14(&mut self) -> _AFRH14W {
_AFRH14W { w: self }
}
- #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh13(&mut self) -> _AFRH13W {
_AFRH13W { w: self }
}
- #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh12(&mut self) -> _AFRH12W {
_AFRH12W { w: self }
}
- #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh11(&mut self) -> _AFRH11W {
_AFRH11W { w: self }
}
- #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh10(&mut self) -> _AFRH10W {
_AFRH10W { w: self }
}
- #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh9(&mut self) -> _AFRH9W {
_AFRH9W { w: self }
}
- #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ( always ) ]
pub fn afrh8(&mut self) -> _AFRH8W {
_AFRH8W { w: self }
}
@@ -137511,8 +137155,7 @@ pub mod i2c3 {
};
DUTYR { bits }
}
- #[doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)" ] # [ inline ( always ) ]
pub fn ccr(&self) -> CCRR {
let bits = {
const MASK: u16 = 4095;
@@ -137544,8 +137187,7 @@ pub mod i2c3 {
pub fn duty(&mut self) -> _DUTYW {
_DUTYW { w: self }
}
- #[doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)" ] # [ inline ( always ) ]
pub fn ccr(&mut self) -> _CCRW {
_CCRW { w: self }
}
@@ -137633,8 +137275,7 @@ pub mod i2c3 {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)" ] # [ inline ( always ) ]
pub fn trise(&self) -> TRISER {
let bits = {
const MASK: u8 = 63;
@@ -137656,8 +137297,7 @@ pub mod i2c3 {
self.bits = bits;
self
}
- #[doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)"]
- #[inline(always)]
+ # [ doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)" ] # [ inline ( always ) ]
pub fn trise(&mut self) -> _TRISEW {
_TRISEW { w: self }
}
@@ -150599,8 +150239,7 @@ pub mod dfsdm1 {
};
AWFSELR { bits }
}
- #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
- #[inline(always)]
+ # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ( always ) ]
pub fn fast(&self) -> FASTR {
let bits = {
const MASK: bool = true;
@@ -150619,8 +150258,7 @@ pub mod dfsdm1 {
};
RCHR { bits }
}
- #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
- #[inline(always)]
+ # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ( always ) ]
pub fn rdmaen(&self) -> RDMAENR {
let bits = {
const MASK: bool = true;
@@ -150629,8 +150267,7 @@ pub mod dfsdm1 {
};
RDMAENR { bits }
}
- #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ( always ) ]
pub fn rsync(&self) -> RSYNCR {
let bits = {
const MASK: bool = true;
@@ -150649,8 +150286,7 @@ pub mod dfsdm1 {
};
RCONTR { bits }
}
- #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ( always ) ]
pub fn rswstart(&self) -> RSWSTARTR {
let bits = {
const MASK: bool = true;
@@ -150668,8 +150304,7 @@ pub mod dfsdm1 {
};
JEXTENR { bits }
}
- #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
- #[inline(always)]
+ # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ( always ) ]
pub fn jextsel(&self) -> JEXTSELR {
let bits = {
const MASK: u8 = 7;
@@ -150678,8 +150313,7 @@ pub mod dfsdm1 {
};
JEXTSELR { bits }
}
- #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
- #[inline(always)]
+ # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ( always ) ]
pub fn jdmaen(&self) -> JDMAENR {
let bits = {
const MASK: bool = true;
@@ -150707,8 +150341,7 @@ pub mod dfsdm1 {
};
JSYNCR { bits }
}
- #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ( always ) ]
pub fn jswstart(&self) -> JSWSTARTR {
let bits = {
const MASK: bool = true;
@@ -150745,8 +150378,7 @@ pub mod dfsdm1 {
pub fn awfsel(&mut self) -> _AWFSELW {
_AWFSELW { w: self }
}
- #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
- #[inline(always)]
+ # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ( always ) ]
pub fn fast(&mut self) -> _FASTW {
_FASTW { w: self }
}
@@ -150755,13 +150387,11 @@ pub mod dfsdm1 {
pub fn rch(&mut self) -> _RCHW {
_RCHW { w: self }
}
- #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
- #[inline(always)]
+ # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ( always ) ]
pub fn rdmaen(&mut self) -> _RDMAENW {
_RDMAENW { w: self }
}
- #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ( always ) ]
pub fn rsync(&mut self) -> _RSYNCW {
_RSYNCW { w: self }
}
@@ -150770,8 +150400,7 @@ pub mod dfsdm1 {
pub fn rcont(&mut self) -> _RCONTW {
_RCONTW { w: self }
}
- #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ( always ) ]
pub fn rswstart(&mut self) -> _RSWSTARTW {
_RSWSTARTW { w: self }
}
@@ -150779,13 +150408,11 @@ pub mod dfsdm1 {
pub fn jexten(&mut self) -> _JEXTENW {
_JEXTENW { w: self }
}
- #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
- #[inline(always)]
+ # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ( always ) ]
pub fn jextsel(&mut self) -> _JEXTSELW {
_JEXTSELW { w: self }
}
- #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
- #[inline(always)]
+ # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ( always ) ]
pub fn jdmaen(&mut self) -> _JDMAENW {
_JDMAENW { w: self }
}
@@ -150798,8 +150425,7 @@ pub mod dfsdm1 {
pub fn jsync(&mut self) -> _JSYNCW {
_JSYNCW { w: self }
}
- #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ( always ) ]
pub fn jswstart(&mut self) -> _JSWSTARTW {
_JSWSTARTW { w: self }
}
@@ -152189,8 +151815,7 @@ pub mod dfsdm1 {
};
FORDR { bits }
}
- #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ( always ) ]
pub fn fosr(&self) -> FOSRR {
let bits = {
const MASK: u16 = 1023;
@@ -152199,8 +151824,7 @@ pub mod dfsdm1 {
};
FOSRR { bits }
}
- #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ( always ) ]
pub fn iosr(&self) -> IOSRR {
let bits = {
const MASK: u8 = 255;
@@ -152227,13 +151851,11 @@ pub mod dfsdm1 {
pub fn ford(&mut self) -> _FORDW {
_FORDW { w: self }
}
- #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ( always ) ]
pub fn fosr(&mut self) -> _FOSRW {
_FOSRW { w: self }
}
- #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ( always ) ]
pub fn iosr(&mut self) -> _IOSRW {
_IOSRW { w: self }
}
@@ -152526,8 +152148,7 @@ pub mod dfsdm1 {
};
AWHTR { bits }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ( always ) ]
pub fn bkawh(&self) -> BKAWHR {
let bits = {
const MASK: u8 = 15;
@@ -152554,8 +152175,7 @@ pub mod dfsdm1 {
pub fn awht(&mut self) -> _AWHTW {
_AWHTW { w: self }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ( always ) ]
pub fn bkawh(&mut self) -> _BKAWHW {
_BKAWHW { w: self }
}
@@ -152679,8 +152299,7 @@ pub mod dfsdm1 {
};
AWLTR { bits }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ( always ) ]
pub fn bkawl(&self) -> BKAWLR {
let bits = {
const MASK: u8 = 15;
@@ -152707,8 +152326,7 @@ pub mod dfsdm1 {
pub fn awlt(&mut self) -> _AWLTW {
_AWLTW { w: self }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ( always ) ]
pub fn bkawl(&mut self) -> _BKAWLW {
_BKAWLW { w: self }
}
@@ -153749,8 +153367,7 @@ pub mod dfsdm1 {
};
AWFSELR { bits }
}
- #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
- #[inline(always)]
+ # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ( always ) ]
pub fn fast(&self) -> FASTR {
let bits = {
const MASK: bool = true;
@@ -153769,8 +153386,7 @@ pub mod dfsdm1 {
};
RCHR { bits }
}
- #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
- #[inline(always)]
+ # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ( always ) ]
pub fn rdmaen(&self) -> RDMAENR {
let bits = {
const MASK: bool = true;
@@ -153779,8 +153395,7 @@ pub mod dfsdm1 {
};
RDMAENR { bits }
}
- #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ( always ) ]
pub fn rsync(&self) -> RSYNCR {
let bits = {
const MASK: bool = true;
@@ -153799,8 +153414,7 @@ pub mod dfsdm1 {
};
RCONTR { bits }
}
- #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ( always ) ]
pub fn rswstart(&self) -> RSWSTARTR {
let bits = {
const MASK: bool = true;
@@ -153818,8 +153432,7 @@ pub mod dfsdm1 {
};
JEXTENR { bits }
}
- #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
- #[inline(always)]
+ # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ( always ) ]
pub fn jextsel(&self) -> JEXTSELR {
let bits = {
const MASK: u8 = 7;
@@ -153828,8 +153441,7 @@ pub mod dfsdm1 {
};
JEXTSELR { bits }
}
- #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
- #[inline(always)]
+ # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ( always ) ]
pub fn jdmaen(&self) -> JDMAENR {
let bits = {
const MASK: bool = true;
@@ -153857,8 +153469,7 @@ pub mod dfsdm1 {
};
JSYNCR { bits }
}
- #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ( always ) ]
pub fn jswstart(&self) -> JSWSTARTR {
let bits = {
const MASK: bool = true;
@@ -153895,8 +153506,7 @@ pub mod dfsdm1 {
pub fn awfsel(&mut self) -> _AWFSELW {
_AWFSELW { w: self }
}
- #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
- #[inline(always)]
+ # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ( always ) ]
pub fn fast(&mut self) -> _FASTW {
_FASTW { w: self }
}
@@ -153905,13 +153515,11 @@ pub mod dfsdm1 {
pub fn rch(&mut self) -> _RCHW {
_RCHW { w: self }
}
- #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
- #[inline(always)]
+ # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ( always ) ]
pub fn rdmaen(&mut self) -> _RDMAENW {
_RDMAENW { w: self }
}
- #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ( always ) ]
pub fn rsync(&mut self) -> _RSYNCW {
_RSYNCW { w: self }
}
@@ -153920,8 +153528,7 @@ pub mod dfsdm1 {
pub fn rcont(&mut self) -> _RCONTW {
_RCONTW { w: self }
}
- #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ( always ) ]
pub fn rswstart(&mut self) -> _RSWSTARTW {
_RSWSTARTW { w: self }
}
@@ -153929,13 +153536,11 @@ pub mod dfsdm1 {
pub fn jexten(&mut self) -> _JEXTENW {
_JEXTENW { w: self }
}
- #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
- #[inline(always)]
+ # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ( always ) ]
pub fn jextsel(&mut self) -> _JEXTSELW {
_JEXTSELW { w: self }
}
- #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
- #[inline(always)]
+ # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ( always ) ]
pub fn jdmaen(&mut self) -> _JDMAENW {
_JDMAENW { w: self }
}
@@ -153948,8 +153553,7 @@ pub mod dfsdm1 {
pub fn jsync(&mut self) -> _JSYNCW {
_JSYNCW { w: self }
}
- #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ( always ) ]
pub fn jswstart(&mut self) -> _JSWSTARTW {
_JSWSTARTW { w: self }
}
@@ -155339,8 +154943,7 @@ pub mod dfsdm1 {
};
FORDR { bits }
}
- #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ( always ) ]
pub fn fosr(&self) -> FOSRR {
let bits = {
const MASK: u16 = 1023;
@@ -155349,8 +154952,7 @@ pub mod dfsdm1 {
};
FOSRR { bits }
}
- #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ( always ) ]
pub fn iosr(&self) -> IOSRR {
let bits = {
const MASK: u8 = 255;
@@ -155377,13 +154979,11 @@ pub mod dfsdm1 {
pub fn ford(&mut self) -> _FORDW {
_FORDW { w: self }
}
- #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ( always ) ]
pub fn fosr(&mut self) -> _FOSRW {
_FOSRW { w: self }
}
- #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ( always ) ]
pub fn iosr(&mut self) -> _IOSRW {
_IOSRW { w: self }
}
@@ -155676,8 +155276,7 @@ pub mod dfsdm1 {
};
AWHTR { bits }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ( always ) ]
pub fn bkawh(&self) -> BKAWHR {
let bits = {
const MASK: u8 = 15;
@@ -155704,8 +155303,7 @@ pub mod dfsdm1 {
pub fn awht(&mut self) -> _AWHTW {
_AWHTW { w: self }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ( always ) ]
pub fn bkawh(&mut self) -> _BKAWHW {
_BKAWHW { w: self }
}
@@ -155829,8 +155427,7 @@ pub mod dfsdm1 {
};
AWLTR { bits }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ( always ) ]
pub fn bkawl(&self) -> BKAWLR {
let bits = {
const MASK: u8 = 15;
@@ -155857,8 +155454,7 @@ pub mod dfsdm1 {
pub fn awlt(&mut self) -> _AWLTW {
_AWLTW { w: self }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ( always ) ]
pub fn bkawl(&mut self) -> _BKAWLW {
_BKAWLW { w: self }
}
@@ -156899,8 +156495,7 @@ pub mod dfsdm1 {
};
AWFSELR { bits }
}
- #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
- #[inline(always)]
+ # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ( always ) ]
pub fn fast(&self) -> FASTR {
let bits = {
const MASK: bool = true;
@@ -156919,8 +156514,7 @@ pub mod dfsdm1 {
};
RCHR { bits }
}
- #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
- #[inline(always)]
+ # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ( always ) ]
pub fn rdmaen(&self) -> RDMAENR {
let bits = {
const MASK: bool = true;
@@ -156929,8 +156523,7 @@ pub mod dfsdm1 {
};
RDMAENR { bits }
}
- #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ( always ) ]
pub fn rsync(&self) -> RSYNCR {
let bits = {
const MASK: bool = true;
@@ -156949,8 +156542,7 @@ pub mod dfsdm1 {
};
RCONTR { bits }
}
- #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ( always ) ]
pub fn rswstart(&self) -> RSWSTARTR {
let bits = {
const MASK: bool = true;
@@ -156968,8 +156560,7 @@ pub mod dfsdm1 {
};
JEXTENR { bits }
}
- #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
- #[inline(always)]
+ # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ( always ) ]
pub fn jextsel(&self) -> JEXTSELR {
let bits = {
const MASK: u8 = 7;
@@ -156978,8 +156569,7 @@ pub mod dfsdm1 {
};
JEXTSELR { bits }
}
- #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
- #[inline(always)]
+ # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ( always ) ]
pub fn jdmaen(&self) -> JDMAENR {
let bits = {
const MASK: bool = true;
@@ -157007,8 +156597,7 @@ pub mod dfsdm1 {
};
JSYNCR { bits }
}
- #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ( always ) ]
pub fn jswstart(&self) -> JSWSTARTR {
let bits = {
const MASK: bool = true;
@@ -157045,8 +156634,7 @@ pub mod dfsdm1 {
pub fn awfsel(&mut self) -> _AWFSELW {
_AWFSELW { w: self }
}
- #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
- #[inline(always)]
+ # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ( always ) ]
pub fn fast(&mut self) -> _FASTW {
_FASTW { w: self }
}
@@ -157055,13 +156643,11 @@ pub mod dfsdm1 {
pub fn rch(&mut self) -> _RCHW {
_RCHW { w: self }
}
- #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
- #[inline(always)]
+ # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ( always ) ]
pub fn rdmaen(&mut self) -> _RDMAENW {
_RDMAENW { w: self }
}
- #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ( always ) ]
pub fn rsync(&mut self) -> _RSYNCW {
_RSYNCW { w: self }
}
@@ -157070,8 +156656,7 @@ pub mod dfsdm1 {
pub fn rcont(&mut self) -> _RCONTW {
_RCONTW { w: self }
}
- #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ( always ) ]
pub fn rswstart(&mut self) -> _RSWSTARTW {
_RSWSTARTW { w: self }
}
@@ -157079,13 +156664,11 @@ pub mod dfsdm1 {
pub fn jexten(&mut self) -> _JEXTENW {
_JEXTENW { w: self }
}
- #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
- #[inline(always)]
+ # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ( always ) ]
pub fn jextsel(&mut self) -> _JEXTSELW {
_JEXTSELW { w: self }
}
- #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
- #[inline(always)]
+ # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ( always ) ]
pub fn jdmaen(&mut self) -> _JDMAENW {
_JDMAENW { w: self }
}
@@ -157098,8 +156681,7 @@ pub mod dfsdm1 {
pub fn jsync(&mut self) -> _JSYNCW {
_JSYNCW { w: self }
}
- #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ( always ) ]
pub fn jswstart(&mut self) -> _JSWSTARTW {
_JSWSTARTW { w: self }
}
@@ -158489,8 +158071,7 @@ pub mod dfsdm1 {
};
FORDR { bits }
}
- #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ( always ) ]
pub fn fosr(&self) -> FOSRR {
let bits = {
const MASK: u16 = 1023;
@@ -158499,8 +158080,7 @@ pub mod dfsdm1 {
};
FOSRR { bits }
}
- #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ( always ) ]
pub fn iosr(&self) -> IOSRR {
let bits = {
const MASK: u8 = 255;
@@ -158527,13 +158107,11 @@ pub mod dfsdm1 {
pub fn ford(&mut self) -> _FORDW {
_FORDW { w: self }
}
- #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ( always ) ]
pub fn fosr(&mut self) -> _FOSRW {
_FOSRW { w: self }
}
- #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ( always ) ]
pub fn iosr(&mut self) -> _IOSRW {
_IOSRW { w: self }
}
@@ -158826,8 +158404,7 @@ pub mod dfsdm1 {
};
AWHTR { bits }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ( always ) ]
pub fn bkawh(&self) -> BKAWHR {
let bits = {
const MASK: u8 = 15;
@@ -158854,8 +158431,7 @@ pub mod dfsdm1 {
pub fn awht(&mut self) -> _AWHTW {
_AWHTW { w: self }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ( always ) ]
pub fn bkawh(&mut self) -> _BKAWHW {
_BKAWHW { w: self }
}
@@ -158979,8 +158555,7 @@ pub mod dfsdm1 {
};
AWLTR { bits }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ( always ) ]
pub fn bkawl(&self) -> BKAWLR {
let bits = {
const MASK: u8 = 15;
@@ -159007,8 +158582,7 @@ pub mod dfsdm1 {
pub fn awlt(&mut self) -> _AWLTW {
_AWLTW { w: self }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ( always ) ]
pub fn bkawl(&mut self) -> _BKAWLW {
_BKAWLW { w: self }
}
@@ -160049,8 +159623,7 @@ pub mod dfsdm1 {
};
AWFSELR { bits }
}
- #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
- #[inline(always)]
+ # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ( always ) ]
pub fn fast(&self) -> FASTR {
let bits = {
const MASK: bool = true;
@@ -160069,8 +159642,7 @@ pub mod dfsdm1 {
};
RCHR { bits }
}
- #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
- #[inline(always)]
+ # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ( always ) ]
pub fn rdmaen(&self) -> RDMAENR {
let bits = {
const MASK: bool = true;
@@ -160079,8 +159651,7 @@ pub mod dfsdm1 {
};
RDMAENR { bits }
}
- #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ( always ) ]
pub fn rsync(&self) -> RSYNCR {
let bits = {
const MASK: bool = true;
@@ -160099,8 +159670,7 @@ pub mod dfsdm1 {
};
RCONTR { bits }
}
- #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ( always ) ]
pub fn rswstart(&self) -> RSWSTARTR {
let bits = {
const MASK: bool = true;
@@ -160118,8 +159688,7 @@ pub mod dfsdm1 {
};
JEXTENR { bits }
}
- #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
- #[inline(always)]
+ # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ( always ) ]
pub fn jextsel(&self) -> JEXTSELR {
let bits = {
const MASK: u8 = 7;
@@ -160128,8 +159697,7 @@ pub mod dfsdm1 {
};
JEXTSELR { bits }
}
- #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
- #[inline(always)]
+ # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ( always ) ]
pub fn jdmaen(&self) -> JDMAENR {
let bits = {
const MASK: bool = true;
@@ -160157,8 +159725,7 @@ pub mod dfsdm1 {
};
JSYNCR { bits }
}
- #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ( always ) ]
pub fn jswstart(&self) -> JSWSTARTR {
let bits = {
const MASK: bool = true;
@@ -160195,8 +159762,7 @@ pub mod dfsdm1 {
pub fn awfsel(&mut self) -> _AWFSELW {
_AWFSELW { w: self }
}
- #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
- #[inline(always)]
+ # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ( always ) ]
pub fn fast(&mut self) -> _FASTW {
_FASTW { w: self }
}
@@ -160205,13 +159771,11 @@ pub mod dfsdm1 {
pub fn rch(&mut self) -> _RCHW {
_RCHW { w: self }
}
- #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
- #[inline(always)]
+ # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ( always ) ]
pub fn rdmaen(&mut self) -> _RDMAENW {
_RDMAENW { w: self }
}
- #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
- #[inline(always)]
+ # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ( always ) ]
pub fn rsync(&mut self) -> _RSYNCW {
_RSYNCW { w: self }
}
@@ -160220,8 +159784,7 @@ pub mod dfsdm1 {
pub fn rcont(&mut self) -> _RCONTW {
_RCONTW { w: self }
}
- #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
- #[inline(always)]
+ # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ( always ) ]
pub fn rswstart(&mut self) -> _RSWSTARTW {
_RSWSTARTW { w: self }
}
@@ -160229,13 +159792,11 @@ pub mod dfsdm1 {
pub fn jexten(&mut self) -> _JEXTENW {
_JEXTENW { w: self }
}
- #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
- #[inline(always)]
+ # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ( always ) ]
pub fn jextsel(&mut self) -> _JEXTSELW {
_JEXTSELW { w: self }
}
- #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
- #[inline(always)]
+ # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ( always ) ]
pub fn jdmaen(&mut self) -> _JDMAENW {
_JDMAENW { w: self }
}
@@ -160248,8 +159809,7 @@ pub mod dfsdm1 {
pub fn jsync(&mut self) -> _JSYNCW {
_JSYNCW { w: self }
}
- #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
- #[inline(always)]
+ # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ( always ) ]
pub fn jswstart(&mut self) -> _JSWSTARTW {
_JSWSTARTW { w: self }
}
@@ -161639,8 +161199,7 @@ pub mod dfsdm1 {
};
FORDR { bits }
}
- #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ( always ) ]
pub fn fosr(&self) -> FOSRR {
let bits = {
const MASK: u16 = 1023;
@@ -161649,8 +161208,7 @@ pub mod dfsdm1 {
};
FOSRR { bits }
}
- #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ( always ) ]
pub fn iosr(&self) -> IOSRR {
let bits = {
const MASK: u8 = 255;
@@ -161677,13 +161235,11 @@ pub mod dfsdm1 {
pub fn ford(&mut self) -> _FORDW {
_FORDW { w: self }
}
- #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
- #[inline(always)]
+ # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ( always ) ]
pub fn fosr(&mut self) -> _FOSRW {
_FOSRW { w: self }
}
- #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
- #[inline(always)]
+ # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ( always ) ]
pub fn iosr(&mut self) -> _IOSRW {
_IOSRW { w: self }
}
@@ -161976,8 +161532,7 @@ pub mod dfsdm1 {
};
AWHTR { bits }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ( always ) ]
pub fn bkawh(&self) -> BKAWHR {
let bits = {
const MASK: u8 = 15;
@@ -162004,8 +161559,7 @@ pub mod dfsdm1 {
pub fn awht(&mut self) -> _AWHTW {
_AWHTW { w: self }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ( always ) ]
pub fn bkawh(&mut self) -> _BKAWHW {
_BKAWHW { w: self }
}
@@ -162129,8 +161683,7 @@ pub mod dfsdm1 {
};
AWLTR { bits }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ( always ) ]
pub fn bkawl(&self) -> BKAWLR {
let bits = {
const MASK: u8 = 15;
@@ -162157,8 +161710,7 @@ pub mod dfsdm1 {
pub fn awlt(&mut self) -> _AWLTW {
_AWLTW { w: self }
}
- #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
- #[inline(always)]
+ # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ( always ) ]
pub fn bkawl(&mut self) -> _BKAWLW {
_BKAWLW { w: self }
}
@@ -310077,51 +309629,14 @@ impl Deref for FSMC {
}
}
#[doc = "USB on the go full speed"]
-pub const OTG_FS_GLOBAL: Peripheral<OTG_FS_GLOBAL> = unsafe { Peripheral::new(1342177280) };
+pub const OTG_FS_GLOBAL: Peripheral<OTG_FS_GLOBAL> =
+ unsafe { Peripheral::new(1342177280) };
#[doc = "USB on the go full speed"]
pub mod otg_fs_global {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - OTG_FS control and status register (OTG_FS_GOTGCTL)"]
- pub fs_gotgctl: FS_GOTGCTL,
- #[doc = "0x04 - OTG_FS interrupt register (OTG_FS_GOTGINT)"]
- pub fs_gotgint: FS_GOTGINT,
- #[doc = "0x08 - OTG_FS AHB configuration register (OTG_FS_GAHBCFG)"]
- pub fs_gahbcfg: FS_GAHBCFG,
- #[doc = "0x0c - OTG_FS USB configuration register (OTG_FS_GUSBCFG)"]
- pub fs_gusbcfg: FS_GUSBCFG,
- #[doc = "0x10 - OTG_FS reset register (OTG_FS_GRSTCTL)"]
- pub fs_grstctl: FS_GRSTCTL,
- #[doc = "0x14 - OTG_FS core interrupt register (OTG_FS_GINTSTS)"]
- pub fs_gintsts: FS_GINTSTS,
- #[doc = "0x18 - OTG_FS interrupt mask register (OTG_FS_GINTMSK)"]
- pub fs_gintmsk: FS_GINTMSK,
- #[doc = "0x1c - OTG_FS Receive status debug read(Device mode)"]
- pub fs_grxstsr_device: FS_GRXSTSR_DEVICE,
- _reserved0: [u8; 4usize],
- #[doc = "0x24 - OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)"]
- pub fs_grxfsiz: FS_GRXFSIZ,
- #[doc = "0x28 - OTG_FS non-periodic transmit FIFO size register (Device mode)"]
- pub fs_gnptxfsiz_device: FS_GNPTXFSIZ_DEVICE,
- #[doc = "0x2c - OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)"]
- pub fs_gnptxsts: FS_GNPTXSTS,
- _reserved1: [u8; 8usize],
- #[doc = "0x38 - OTG_FS general core configuration register (OTG_FS_GCCFG)"]
- pub fs_gccfg: FS_GCCFG,
- #[doc = "0x3c - core ID register"]
- pub fs_cid: FS_CID,
- _reserved2: [u8; 192usize],
- #[doc = "0x100 - OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)"]
- pub fs_hptxfsiz: FS_HPTXFSIZ,
- #[doc = "0x104 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)"]
- pub fs_dieptxf1: FS_DIEPTXF1,
- #[doc = "0x108 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)"]
- pub fs_dieptxf2: FS_DIEPTXF2,
- #[doc = "0x10c - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)"]
- pub fs_dieptxf3: FS_DIEPTXF3,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - OTG_FS control and status register (OTG_FS_GOTGCTL)" ] pub fs_gotgctl : FS_GOTGCTL , # [ doc = "0x04 - OTG_FS interrupt register (OTG_FS_GOTGINT)" ] pub fs_gotgint : FS_GOTGINT , # [ doc = "0x08 - OTG_FS AHB configuration register (OTG_FS_GAHBCFG)" ] pub fs_gahbcfg : FS_GAHBCFG , # [ doc = "0x0c - OTG_FS USB configuration register (OTG_FS_GUSBCFG)" ] pub fs_gusbcfg : FS_GUSBCFG , # [ doc = "0x10 - OTG_FS reset register (OTG_FS_GRSTCTL)" ] pub fs_grstctl : FS_GRSTCTL , # [ doc = "0x14 - OTG_FS core interrupt register (OTG_FS_GINTSTS)" ] pub fs_gintsts : FS_GINTSTS , # [ doc = "0x18 - OTG_FS interrupt mask register (OTG_FS_GINTMSK)" ] pub fs_gintmsk : FS_GINTMSK , # [ doc = "0x1c - OTG_FS Receive status debug read(Device mode)" ] pub fs_grxstsr_device : FS_GRXSTSR_DEVICE , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x24 - OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)" ] pub fs_grxfsiz : FS_GRXFSIZ , # [ doc = "0x28 - OTG_FS non-periodic transmit FIFO size register (Device mode)" ] pub fs_gnptxfsiz_device : FS_GNPTXFSIZ_DEVICE , # [ doc = "0x2c - OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)" ] pub fs_gnptxsts : FS_GNPTXSTS , _reserved1 : [ u8 ; 8usize ] , # [ doc = "0x38 - OTG_FS general core configuration register (OTG_FS_GCCFG)" ] pub fs_gccfg : FS_GCCFG , # [ doc = "0x3c - core ID register" ] pub fs_cid : FS_CID , _reserved2 : [ u8 ; 192usize ] , # [ doc = "0x100 - OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)" ] pub fs_hptxfsiz : FS_HPTXFSIZ , # [ doc = "0x104 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)" ] pub fs_dieptxf1 : FS_DIEPTXF1 , # [ doc = "0x108 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)" ] pub fs_dieptxf2 : FS_DIEPTXF2 , # [ doc = "0x10c - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)" ] pub fs_dieptxf3 : FS_DIEPTXF3 , }
#[doc = "OTG_FS control and status register (OTG_FS_GOTGCTL)"]
pub struct FS_GOTGCTL {
register: VolatileCell<u32>,
@@ -314800,8 +314315,7 @@ pub mod otg_fs_global {
};
DISCINTR { bits }
}
- #[doc = "Bit 30 - Session request/new session detected interrupt mask"]
- #[inline(always)]
+ # [ doc = "Bit 30 - Session request/new session detected interrupt mask" ] # [ inline ( always ) ]
pub fn srqim(&self) -> SRQIMR {
let bits = {
const MASK: bool = true;
@@ -314942,8 +314456,7 @@ pub mod otg_fs_global {
pub fn discint(&mut self) -> _DISCINTW {
_DISCINTW { w: self }
}
- #[doc = "Bit 30 - Session request/new session detected interrupt mask"]
- #[inline(always)]
+ # [ doc = "Bit 30 - Session request/new session detected interrupt mask" ] # [ inline ( always ) ]
pub fn srqim(&mut self) -> _SRQIMW {
_SRQIMW { w: self }
}
@@ -315636,11 +315149,11 @@ pub mod otg_fs_global {
}
}
}
- #[doc = "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)"]
+ # [ doc = "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)" ]
pub struct FS_GNPTXSTS {
register: VolatileCell<u32>,
}
- #[doc = "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)"]
+ # [ doc = "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)" ]
pub mod fs_gnptxsts {
#[doc = r" Value read from the register"]
pub struct R {
@@ -315704,8 +315217,7 @@ pub mod otg_fs_global {
};
NPTXFSAVR { bits }
}
- #[doc = "Bits 16:23 - Non-periodic transmit request queue space available"]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Non-periodic transmit request queue space available" ] # [ inline ( always ) ]
pub fn nptqxsav(&self) -> NPTQXSAVR {
let bits = {
const MASK: u8 = 255;
@@ -315714,8 +315226,7 @@ pub mod otg_fs_global {
};
NPTQXSAVR { bits }
}
- #[doc = "Bits 24:30 - Top of the non-periodic transmit request queue"]
- #[inline(always)]
+ # [ doc = "Bits 24:30 - Top of the non-periodic transmit request queue" ] # [ inline ( always ) ]
pub fn nptxqtop(&self) -> NPTXQTOPR {
let bits = {
const MASK: u8 = 127;
@@ -316652,11 +316163,11 @@ pub mod otg_fs_global {
}
}
}
- #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)"]
+ # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)" ]
pub struct FS_DIEPTXF1 {
register: VolatileCell<u32>,
}
- #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)"]
+ # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)" ]
pub mod fs_dieptxf1 {
#[doc = r" Value read from the register"]
pub struct R {
@@ -316805,11 +316316,11 @@ pub mod otg_fs_global {
}
}
}
- #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)"]
+ # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)" ]
pub struct FS_DIEPTXF2 {
register: VolatileCell<u32>,
}
- #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)"]
+ # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)" ]
pub mod fs_dieptxf2 {
#[doc = r" Value read from the register"]
pub struct R {
@@ -316958,11 +316469,11 @@ pub mod otg_fs_global {
}
}
}
- #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)"]
+ # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)" ]
pub struct FS_DIEPTXF3 {
register: VolatileCell<u32>,
}
- #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)"]
+ # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)" ]
pub mod fs_dieptxf3 {
#[doc = r" Value read from the register"]
pub struct R {
@@ -317123,110 +316634,14 @@ impl Deref for OTG_FS_GLOBAL {
}
}
#[doc = "USB on the go full speed"]
-pub const OTG_FS_HOST: Peripheral<OTG_FS_HOST> = unsafe { Peripheral::new(1342178304) };
+pub const OTG_FS_HOST: Peripheral<OTG_FS_HOST> =
+ unsafe { Peripheral::new(1342178304) };
#[doc = "USB on the go full speed"]
pub mod otg_fs_host {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - OTG_FS host configuration register (OTG_FS_HCFG)"]
- pub fs_hcfg: FS_HCFG,
- #[doc = "0x04 - OTG_FS Host frame interval register"]
- pub hfir: HFIR,
- #[doc = "0x08 - OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)"]
- pub fs_hfnum: FS_HFNUM,
- _reserved0: [u8; 4usize],
- #[doc = "0x10 - OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)"]
- pub fs_hptxsts: FS_HPTXSTS,
- #[doc = "0x14 - OTG_FS Host all channels interrupt register"]
- pub haint: HAINT,
- #[doc = "0x18 - OTG_FS host all channels interrupt mask register"]
- pub haintmsk: HAINTMSK,
- _reserved1: [u8; 36usize],
- #[doc = "0x40 - OTG_FS host port control and status register (OTG_FS_HPRT)"]
- pub fs_hprt: FS_HPRT,
- _reserved2: [u8; 188usize],
- #[doc = "0x100 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)"]
- pub fs_hcchar0: FS_HCCHAR0,
- _reserved3: [u8; 4usize],
- #[doc = "0x108 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)"]
- pub fs_hcint0: FS_HCINT0,
- #[doc = "0x10c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)"]
- pub fs_hcintmsk0: FS_HCINTMSK0,
- #[doc = "0x110 - OTG_FS host channel-0 transfer size register"]
- pub fs_hctsiz0: FS_HCTSIZ0,
- _reserved4: [u8; 12usize],
- #[doc = "0x120 - OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)"]
- pub fs_hcchar1: FS_HCCHAR1,
- _reserved5: [u8; 4usize],
- #[doc = "0x128 - OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)"]
- pub fs_hcint1: FS_HCINT1,
- #[doc = "0x12c - OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)"]
- pub fs_hcintmsk1: FS_HCINTMSK1,
- #[doc = "0x130 - OTG_FS host channel-1 transfer size register"]
- pub fs_hctsiz1: FS_HCTSIZ1,
- _reserved6: [u8; 12usize],
- #[doc = "0x140 - OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)"]
- pub fs_hcchar2: FS_HCCHAR2,
- _reserved7: [u8; 4usize],
- #[doc = "0x148 - OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)"]
- pub fs_hcint2: FS_HCINT2,
- #[doc = "0x14c - OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)"]
- pub fs_hcintmsk2: FS_HCINTMSK2,
- #[doc = "0x150 - OTG_FS host channel-2 transfer size register"]
- pub fs_hctsiz2: FS_HCTSIZ2,
- _reserved8: [u8; 12usize],
- #[doc = "0x160 - OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)"]
- pub fs_hcchar3: FS_HCCHAR3,
- _reserved9: [u8; 4usize],
- #[doc = "0x168 - OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)"]
- pub fs_hcint3: FS_HCINT3,
- #[doc = "0x16c - OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)"]
- pub fs_hcintmsk3: FS_HCINTMSK3,
- #[doc = "0x170 - OTG_FS host channel-3 transfer size register"]
- pub fs_hctsiz3: FS_HCTSIZ3,
- _reserved10: [u8; 12usize],
- #[doc = "0x180 - OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)"]
- pub fs_hcchar4: FS_HCCHAR4,
- _reserved11: [u8; 4usize],
- #[doc = "0x188 - OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)"]
- pub fs_hcint4: FS_HCINT4,
- #[doc = "0x18c - OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)"]
- pub fs_hcintmsk4: FS_HCINTMSK4,
- #[doc = "0x190 - OTG_FS host channel-x transfer size register"]
- pub fs_hctsiz4: FS_HCTSIZ4,
- _reserved12: [u8; 12usize],
- #[doc = "0x1a0 - OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)"]
- pub fs_hcchar5: FS_HCCHAR5,
- _reserved13: [u8; 4usize],
- #[doc = "0x1a8 - OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)"]
- pub fs_hcint5: FS_HCINT5,
- #[doc = "0x1ac - OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)"]
- pub fs_hcintmsk5: FS_HCINTMSK5,
- #[doc = "0x1b0 - OTG_FS host channel-5 transfer size register"]
- pub fs_hctsiz5: FS_HCTSIZ5,
- _reserved14: [u8; 12usize],
- #[doc = "0x1c0 - OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)"]
- pub fs_hcchar6: FS_HCCHAR6,
- _reserved15: [u8; 4usize],
- #[doc = "0x1c8 - OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)"]
- pub fs_hcint6: FS_HCINT6,
- #[doc = "0x1cc - OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)"]
- pub fs_hcintmsk6: FS_HCINTMSK6,
- #[doc = "0x1d0 - OTG_FS host channel-6 transfer size register"]
- pub fs_hctsiz6: FS_HCTSIZ6,
- _reserved16: [u8; 12usize],
- #[doc = "0x1e0 - OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)"]
- pub fs_hcchar7: FS_HCCHAR7,
- _reserved17: [u8; 4usize],
- #[doc = "0x1e8 - OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)"]
- pub fs_hcint7: FS_HCINT7,
- #[doc = "0x1ec - OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)"]
- pub fs_hcintmsk7: FS_HCINTMSK7,
- #[doc = "0x1f0 - OTG_FS host channel-7 transfer size register"]
- pub fs_hctsiz7: FS_HCTSIZ7,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - OTG_FS host configuration register (OTG_FS_HCFG)" ] pub fs_hcfg : FS_HCFG , # [ doc = "0x04 - OTG_FS Host frame interval register" ] pub hfir : HFIR , # [ doc = "0x08 - OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)" ] pub fs_hfnum : FS_HFNUM , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x10 - OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)" ] pub fs_hptxsts : FS_HPTXSTS , # [ doc = "0x14 - OTG_FS Host all channels interrupt register" ] pub haint : HAINT , # [ doc = "0x18 - OTG_FS host all channels interrupt mask register" ] pub haintmsk : HAINTMSK , _reserved1 : [ u8 ; 36usize ] , # [ doc = "0x40 - OTG_FS host port control and status register (OTG_FS_HPRT)" ] pub fs_hprt : FS_HPRT , _reserved2 : [ u8 ; 188usize ] , # [ doc = "0x100 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)" ] pub fs_hcchar0 : FS_HCCHAR0 , _reserved3 : [ u8 ; 4usize ] , # [ doc = "0x108 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)" ] pub fs_hcint0 : FS_HCINT0 , # [ doc = "0x10c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)" ] pub fs_hcintmsk0 : FS_HCINTMSK0 , # [ doc = "0x110 - OTG_FS host channel-0 transfer size register" ] pub fs_hctsiz0 : FS_HCTSIZ0 , _reserved4 : [ u8 ; 12usize ] , # [ doc = "0x120 - OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)" ] pub fs_hcchar1 : FS_HCCHAR1 , _reserved5 : [ u8 ; 4usize ] , # [ doc = "0x128 - OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)" ] pub fs_hcint1 : FS_HCINT1 , # [ doc = "0x12c - OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)" ] pub fs_hcintmsk1 : FS_HCINTMSK1 , # [ doc = "0x130 - OTG_FS host channel-1 transfer size register" ] pub fs_hctsiz1 : FS_HCTSIZ1 , _reserved6 : [ u8 ; 12usize ] , # [ doc = "0x140 - OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)" ] pub fs_hcchar2 : FS_HCCHAR2 , _reserved7 : [ u8 ; 4usize ] , # [ doc = "0x148 - OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)" ] pub fs_hcint2 : FS_HCINT2 , # [ doc = "0x14c - OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)" ] pub fs_hcintmsk2 : FS_HCINTMSK2 , # [ doc = "0x150 - OTG_FS host channel-2 transfer size register" ] pub fs_hctsiz2 : FS_HCTSIZ2 , _reserved8 : [ u8 ; 12usize ] , # [ doc = "0x160 - OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)" ] pub fs_hcchar3 : FS_HCCHAR3 , _reserved9 : [ u8 ; 4usize ] , # [ doc = "0x168 - OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)" ] pub fs_hcint3 : FS_HCINT3 , # [ doc = "0x16c - OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)" ] pub fs_hcintmsk3 : FS_HCINTMSK3 , # [ doc = "0x170 - OTG_FS host channel-3 transfer size register" ] pub fs_hctsiz3 : FS_HCTSIZ3 , _reserved10 : [ u8 ; 12usize ] , # [ doc = "0x180 - OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)" ] pub fs_hcchar4 : FS_HCCHAR4 , _reserved11 : [ u8 ; 4usize ] , # [ doc = "0x188 - OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)" ] pub fs_hcint4 : FS_HCINT4 , # [ doc = "0x18c - OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)" ] pub fs_hcintmsk4 : FS_HCINTMSK4 , # [ doc = "0x190 - OTG_FS host channel-x transfer size register" ] pub fs_hctsiz4 : FS_HCTSIZ4 , _reserved12 : [ u8 ; 12usize ] , # [ doc = "0x1a0 - OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)" ] pub fs_hcchar5 : FS_HCCHAR5 , _reserved13 : [ u8 ; 4usize ] , # [ doc = "0x1a8 - OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)" ] pub fs_hcint5 : FS_HCINT5 , # [ doc = "0x1ac - OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)" ] pub fs_hcintmsk5 : FS_HCINTMSK5 , # [ doc = "0x1b0 - OTG_FS host channel-5 transfer size register" ] pub fs_hctsiz5 : FS_HCTSIZ5 , _reserved14 : [ u8 ; 12usize ] , # [ doc = "0x1c0 - OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)" ] pub fs_hcchar6 : FS_HCCHAR6 , _reserved15 : [ u8 ; 4usize ] , # [ doc = "0x1c8 - OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)" ] pub fs_hcint6 : FS_HCINT6 , # [ doc = "0x1cc - OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)" ] pub fs_hcintmsk6 : FS_HCINTMSK6 , # [ doc = "0x1d0 - OTG_FS host channel-6 transfer size register" ] pub fs_hctsiz6 : FS_HCTSIZ6 , _reserved16 : [ u8 ; 12usize ] , # [ doc = "0x1e0 - OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)" ] pub fs_hcchar7 : FS_HCCHAR7 , _reserved17 : [ u8 ; 4usize ] , # [ doc = "0x1e8 - OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)" ] pub fs_hcint7 : FS_HCINT7 , # [ doc = "0x1ec - OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)" ] pub fs_hcintmsk7 : FS_HCINTMSK7 , # [ doc = "0x1f0 - OTG_FS host channel-7 transfer size register" ] pub fs_hctsiz7 : FS_HCTSIZ7 , }
#[doc = "OTG_FS host configuration register (OTG_FS_HCFG)"]
pub struct FS_HCFG {
register: VolatileCell<u32>,
@@ -317482,11 +316897,11 @@ pub mod otg_fs_host {
}
}
}
- #[doc = "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)"]
+ # [ doc = "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)" ]
pub struct FS_HFNUM {
register: VolatileCell<u32>,
}
- #[doc = "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)"]
+ # [ doc = "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)" ]
pub mod fs_hfnum {
#[doc = r" Value read from the register"]
pub struct R {
@@ -317551,11 +316966,11 @@ pub mod otg_fs_host {
}
}
}
- #[doc = "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)"]
+ # [ doc = "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)" ]
pub struct FS_HPTXSTS {
register: VolatileCell<u32>,
}
- #[doc = "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)"]
+ # [ doc = "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)" ]
pub mod fs_hptxsts {
#[doc = r" Value read from the register"]
pub struct R {
@@ -317665,8 +317080,7 @@ pub mod otg_fs_host {
};
PTXFSAVLR { bits }
}
- #[doc = "Bits 16:23 - Periodic transmit request queue space available"]
- #[inline(always)]
+ # [ doc = "Bits 16:23 - Periodic transmit request queue space available" ] # [ inline ( always ) ]
pub fn ptxqsav(&self) -> PTXQSAVR {
let bits = {
const MASK: u8 = 255;
@@ -334789,121 +334203,14 @@ impl Deref for OTG_FS_HOST {
}
}
#[doc = "USB on the go full speed"]
-pub const OTG_FS_DEVICE: Peripheral<OTG_FS_DEVICE> = unsafe { Peripheral::new(1342179328) };
+pub const OTG_FS_DEVICE: Peripheral<OTG_FS_DEVICE> =
+ unsafe { Peripheral::new(1342179328) };
#[doc = "USB on the go full speed"]
pub mod otg_fs_device {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - OTG_FS device configuration register (OTG_FS_DCFG)"]
- pub fs_dcfg: FS_DCFG,
- #[doc = "0x04 - OTG_FS device control register (OTG_FS_DCTL)"]
- pub fs_dctl: FS_DCTL,
- #[doc = "0x08 - OTG_FS device status register (OTG_FS_DSTS)"]
- pub fs_dsts: FS_DSTS,
- _reserved0: [u8; 4usize],
- #[doc = "0x10 - OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)"]
- pub fs_diepmsk: FS_DIEPMSK,
- #[doc = "0x14 - OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)"]
- pub fs_doepmsk: FS_DOEPMSK,
- #[doc = "0x18 - OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)"]
- pub fs_daint: FS_DAINT,
- #[doc = "0x1c - OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)"]
- pub fs_daintmsk: FS_DAINTMSK,
- _reserved1: [u8; 8usize],
- #[doc = "0x28 - OTG_FS device VBUS discharge time register"]
- pub dvbusdis: DVBUSDIS,
- #[doc = "0x2c - OTG_FS device VBUS pulsing time register"]
- pub dvbuspulse: DVBUSPULSE,
- _reserved2: [u8; 4usize],
- #[doc = "0x34 - OTG_FS device IN endpoint FIFO empty interrupt mask register"]
- pub diepempmsk: DIEPEMPMSK,
- _reserved3: [u8; 200usize],
- #[doc = "0x100 - OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)"]
- pub fs_diepctl0: FS_DIEPCTL0,
- _reserved4: [u8; 4usize],
- #[doc = "0x108 - device endpoint-x interrupt register"]
- pub diepint0: DIEPINT0,
- _reserved5: [u8; 4usize],
- #[doc = "0x110 - device endpoint-0 transfer size register"]
- pub dieptsiz0: DIEPTSIZ0,
- _reserved6: [u8; 4usize],
- #[doc = "0x118 - OTG_FS device IN endpoint transmit FIFO status register"]
- pub dtxfsts0: DTXFSTS0,
- _reserved7: [u8; 4usize],
- #[doc = "0x120 - OTG device endpoint-1 control register"]
- pub diepctl1: DIEPCTL1,
- _reserved8: [u8; 4usize],
- #[doc = "0x128 - device endpoint-1 interrupt register"]
- pub diepint1: DIEPINT1,
- _reserved9: [u8; 4usize],
- #[doc = "0x130 - device endpoint-1 transfer size register"]
- pub dieptsiz1: DIEPTSIZ1,
- _reserved10: [u8; 4usize],
- #[doc = "0x138 - OTG_FS device IN endpoint transmit FIFO status register"]
- pub dtxfsts1: DTXFSTS1,
- _reserved11: [u8; 4usize],
- #[doc = "0x140 - OTG device endpoint-2 control register"]
- pub diepctl2: DIEPCTL2,
- _reserved12: [u8; 4usize],
- #[doc = "0x148 - device endpoint-2 interrupt register"]
- pub diepint2: DIEPINT2,
- _reserved13: [u8; 4usize],
- #[doc = "0x150 - device endpoint-2 transfer size register"]
- pub dieptsiz2: DIEPTSIZ2,
- _reserved14: [u8; 4usize],
- #[doc = "0x158 - OTG_FS device IN endpoint transmit FIFO status register"]
- pub dtxfsts2: DTXFSTS2,
- _reserved15: [u8; 4usize],
- #[doc = "0x160 - OTG device endpoint-3 control register"]
- pub diepctl3: DIEPCTL3,
- _reserved16: [u8; 4usize],
- #[doc = "0x168 - device endpoint-3 interrupt register"]
- pub diepint3: DIEPINT3,
- _reserved17: [u8; 4usize],
- #[doc = "0x170 - device endpoint-3 transfer size register"]
- pub dieptsiz3: DIEPTSIZ3,
- _reserved18: [u8; 4usize],
- #[doc = "0x178 - OTG_FS device IN endpoint transmit FIFO status register"]
- pub dtxfsts3: DTXFSTS3,
- _reserved19: [u8; 388usize],
- #[doc = "0x300 - device endpoint-0 control register"]
- pub doepctl0: DOEPCTL0,
- _reserved20: [u8; 4usize],
- #[doc = "0x308 - device endpoint-0 interrupt register"]
- pub doepint0: DOEPINT0,
- _reserved21: [u8; 4usize],
- #[doc = "0x310 - device OUT endpoint-0 transfer size register"]
- pub doeptsiz0: DOEPTSIZ0,
- _reserved22: [u8; 12usize],
- #[doc = "0x320 - device endpoint-1 control register"]
- pub doepctl1: DOEPCTL1,
- _reserved23: [u8; 4usize],
- #[doc = "0x328 - device endpoint-1 interrupt register"]
- pub doepint1: DOEPINT1,
- _reserved24: [u8; 4usize],
- #[doc = "0x330 - device OUT endpoint-1 transfer size register"]
- pub doeptsiz1: DOEPTSIZ1,
- _reserved25: [u8; 12usize],
- #[doc = "0x340 - device endpoint-2 control register"]
- pub doepctl2: DOEPCTL2,
- _reserved26: [u8; 4usize],
- #[doc = "0x348 - device endpoint-2 interrupt register"]
- pub doepint2: DOEPINT2,
- _reserved27: [u8; 4usize],
- #[doc = "0x350 - device OUT endpoint-2 transfer size register"]
- pub doeptsiz2: DOEPTSIZ2,
- _reserved28: [u8; 12usize],
- #[doc = "0x360 - device endpoint-3 control register"]
- pub doepctl3: DOEPCTL3,
- _reserved29: [u8; 4usize],
- #[doc = "0x368 - device endpoint-3 interrupt register"]
- pub doepint3: DOEPINT3,
- _reserved30: [u8; 4usize],
- #[doc = "0x370 - device OUT endpoint-3 transfer size register"]
- pub doeptsiz3: DOEPTSIZ3,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - OTG_FS device configuration register (OTG_FS_DCFG)" ] pub fs_dcfg : FS_DCFG , # [ doc = "0x04 - OTG_FS device control register (OTG_FS_DCTL)" ] pub fs_dctl : FS_DCTL , # [ doc = "0x08 - OTG_FS device status register (OTG_FS_DSTS)" ] pub fs_dsts : FS_DSTS , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x10 - OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)" ] pub fs_diepmsk : FS_DIEPMSK , # [ doc = "0x14 - OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)" ] pub fs_doepmsk : FS_DOEPMSK , # [ doc = "0x18 - OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)" ] pub fs_daint : FS_DAINT , # [ doc = "0x1c - OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)" ] pub fs_daintmsk : FS_DAINTMSK , _reserved1 : [ u8 ; 8usize ] , # [ doc = "0x28 - OTG_FS device VBUS discharge time register" ] pub dvbusdis : DVBUSDIS , # [ doc = "0x2c - OTG_FS device VBUS pulsing time register" ] pub dvbuspulse : DVBUSPULSE , _reserved2 : [ u8 ; 4usize ] , # [ doc = "0x34 - OTG_FS device IN endpoint FIFO empty interrupt mask register" ] pub diepempmsk : DIEPEMPMSK , _reserved3 : [ u8 ; 200usize ] , # [ doc = "0x100 - OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)" ] pub fs_diepctl0 : FS_DIEPCTL0 , _reserved4 : [ u8 ; 4usize ] , # [ doc = "0x108 - device endpoint-x interrupt register" ] pub diepint0 : DIEPINT0 , _reserved5 : [ u8 ; 4usize ] , # [ doc = "0x110 - device endpoint-0 transfer size register" ] pub dieptsiz0 : DIEPTSIZ0 , _reserved6 : [ u8 ; 4usize ] , # [ doc = "0x118 - OTG_FS device IN endpoint transmit FIFO status register" ] pub dtxfsts0 : DTXFSTS0 , _reserved7 : [ u8 ; 4usize ] , # [ doc = "0x120 - OTG device endpoint-1 control register" ] pub diepctl1 : DIEPCTL1 , _reserved8 : [ u8 ; 4usize ] , # [ doc = "0x128 - device endpoint-1 interrupt register" ] pub diepint1 : DIEPINT1 , _reserved9 : [ u8 ; 4usize ] , # [ doc = "0x130 - device endpoint-1 transfer size register" ] pub dieptsiz1 : DIEPTSIZ1 , _reserved10 : [ u8 ; 4usize ] , # [ doc = "0x138 - OTG_FS device IN endpoint transmit FIFO status register" ] pub dtxfsts1 : DTXFSTS1 , _reserved11 : [ u8 ; 4usize ] , # [ doc = "0x140 - OTG device endpoint-2 control register" ] pub diepctl2 : DIEPCTL2 , _reserved12 : [ u8 ; 4usize ] , # [ doc = "0x148 - device endpoint-2 interrupt register" ] pub diepint2 : DIEPINT2 , _reserved13 : [ u8 ; 4usize ] , # [ doc = "0x150 - device endpoint-2 transfer size register" ] pub dieptsiz2 : DIEPTSIZ2 , _reserved14 : [ u8 ; 4usize ] , # [ doc = "0x158 - OTG_FS device IN endpoint transmit FIFO status register" ] pub dtxfsts2 : DTXFSTS2 , _reserved15 : [ u8 ; 4usize ] , # [ doc = "0x160 - OTG device endpoint-3 control register" ] pub diepctl3 : DIEPCTL3 , _reserved16 : [ u8 ; 4usize ] , # [ doc = "0x168 - device endpoint-3 interrupt register" ] pub diepint3 : DIEPINT3 , _reserved17 : [ u8 ; 4usize ] , # [ doc = "0x170 - device endpoint-3 transfer size register" ] pub dieptsiz3 : DIEPTSIZ3 , _reserved18 : [ u8 ; 4usize ] , # [ doc = "0x178 - OTG_FS device IN endpoint transmit FIFO status register" ] pub dtxfsts3 : DTXFSTS3 , _reserved19 : [ u8 ; 388usize ] , # [ doc = "0x300 - device endpoint-0 control register" ] pub doepctl0 : DOEPCTL0 , _reserved20 : [ u8 ; 4usize ] , # [ doc = "0x308 - device endpoint-0 interrupt register" ] pub doepint0 : DOEPINT0 , _reserved21 : [ u8 ; 4usize ] , # [ doc = "0x310 - device OUT endpoint-0 transfer size register" ] pub doeptsiz0 : DOEPTSIZ0 , _reserved22 : [ u8 ; 12usize ] , # [ doc = "0x320 - device endpoint-1 control register" ] pub doepctl1 : DOEPCTL1 , _reserved23 : [ u8 ; 4usize ] , # [ doc = "0x328 - device endpoint-1 interrupt register" ] pub doepint1 : DOEPINT1 , _reserved24 : [ u8 ; 4usize ] , # [ doc = "0x330 - device OUT endpoint-1 transfer size register" ] pub doeptsiz1 : DOEPTSIZ1 , _reserved25 : [ u8 ; 12usize ] , # [ doc = "0x340 - device endpoint-2 control register" ] pub doepctl2 : DOEPCTL2 , _reserved26 : [ u8 ; 4usize ] , # [ doc = "0x348 - device endpoint-2 interrupt register" ] pub doepint2 : DOEPINT2 , _reserved27 : [ u8 ; 4usize ] , # [ doc = "0x350 - device OUT endpoint-2 transfer size register" ] pub doeptsiz2 : DOEPTSIZ2 , _reserved28 : [ u8 ; 12usize ] , # [ doc = "0x360 - device endpoint-3 control register" ] pub doepctl3 : DOEPCTL3 , _reserved29 : [ u8 ; 4usize ] , # [ doc = "0x368 - device endpoint-3 interrupt register" ] pub doepint3 : DOEPINT3 , _reserved30 : [ u8 ; 4usize ] , # [ doc = "0x370 - device OUT endpoint-3 transfer size register" ] pub doeptsiz3 : DOEPTSIZ3 , }
#[doc = "OTG_FS device configuration register (OTG_FS_DCFG)"]
pub struct FS_DCFG {
register: VolatileCell<u32>,
@@ -335896,11 +335203,11 @@ pub mod otg_fs_device {
}
}
}
- #[doc = "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)"]
+ # [ doc = "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)" ]
pub struct FS_DIEPMSK {
register: VolatileCell<u32>,
}
- #[doc = "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)"]
+ # [ doc = "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)" ]
pub mod fs_diepmsk {
#[doc = r" Value read from the register"]
pub struct R {
@@ -336321,11 +335628,11 @@ pub mod otg_fs_device {
}
}
}
- #[doc = "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)"]
+ # [ doc = "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)" ]
pub struct FS_DOEPMSK {
register: VolatileCell<u32>,
}
- #[doc = "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)"]
+ # [ doc = "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)" ]
pub mod fs_doepmsk {
#[doc = r" Value read from the register"]
pub struct R {
@@ -337186,11 +336493,11 @@ pub mod otg_fs_device {
}
}
}
- #[doc = "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)"]
+ # [ doc = "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)" ]
pub struct FS_DIEPCTL0 {
register: VolatileCell<u32>,
}
- #[doc = "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)"]
+ # [ doc = "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)" ]
pub mod fs_diepctl0 {
#[doc = r" Value read from the register"]
pub struct R {
@@ -346470,16 +345777,14 @@ impl Deref for OTG_FS_DEVICE {
}
}
#[doc = "USB on the go full speed"]
-pub const OTG_FS_PWRCLK: Peripheral<OTG_FS_PWRCLK> = unsafe { Peripheral::new(1342180864) };
+pub const OTG_FS_PWRCLK: Peripheral<OTG_FS_PWRCLK> =
+ unsafe { Peripheral::new(1342180864) };
#[doc = "USB on the go full speed"]
pub mod otg_fs_pwrclk {
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
- pub struct RegisterBlock {
- #[doc = "0x00 - OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)"]
- pub fs_pcgcctl: FS_PCGCCTL,
- }
+ pub struct RegisterBlock { # [ doc = "0x00 - OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)" ] pub fs_pcgcctl : FS_PCGCCTL , }
#[doc = "OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)"]
pub struct FS_PCGCCTL {
register: VolatileCell<u32>,
@@ -352995,8 +352300,7 @@ pub mod dac {
};
MAMP2R { bits }
}
- #[doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable"]
- #[inline(always)]
+ # [ doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable" ] # [ inline ( always ) ]
pub fn wave2(&self) -> WAVE2R {
let bits = {
const MASK: u8 = 3;
@@ -353075,8 +352379,7 @@ pub mod dac {
};
MAMP1R { bits }
}
- #[doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable"]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable" ] # [ inline ( always ) ]
pub fn wave1(&self) -> WAVE1R {
let bits = {
const MASK: u8 = 3;
@@ -353153,8 +352456,7 @@ pub mod dac {
pub fn mamp2(&mut self) -> _MAMP2W {
_MAMP2W { w: self }
}
- #[doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable"]
- #[inline(always)]
+ # [ doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable" ] # [ inline ( always ) ]
pub fn wave2(&mut self) -> _WAVE2W {
_WAVE2W { w: self }
}
@@ -353193,8 +352495,7 @@ pub mod dac {
pub fn mamp1(&mut self) -> _MAMP1W {
_MAMP1W { w: self }
}
- #[doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable"]
- #[inline(always)]
+ # [ doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable" ] # [ inline ( always ) ]
pub fn wave1(&mut self) -> _WAVE1W {
_WAVE1W { w: self }
}
@@ -356888,8 +356189,7 @@ pub mod sai {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 6 - Late frame synchronization detection interrupt enable"]
- #[inline(always)]
+ # [ doc = "Bit 6 - Late frame synchronization detection interrupt enable" ] # [ inline ( always ) ]
pub fn lfsdetie(&self) -> LFSDETIER {
let bits = {
const MASK: bool = true;
@@ -356898,8 +356198,7 @@ pub mod sai {
};
LFSDETIER { bits }
}
- #[doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable" ] # [ inline ( always ) ]
pub fn afsdetie(&self) -> AFSDETIER {
let bits = {
const MASK: bool = true;
@@ -356971,13 +356270,11 @@ pub mod sai {
self.bits = bits;
self
}
- #[doc = "Bit 6 - Late frame synchronization detection interrupt enable"]
- #[inline(always)]
+ # [ doc = "Bit 6 - Late frame synchronization detection interrupt enable" ] # [ inline ( always ) ]
pub fn lfsdetie(&mut self) -> _LFSDETIEW {
_LFSDETIEW { w: self }
}
- #[doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable" ] # [ inline ( always ) ]
pub fn afsdetie(&mut self) -> _AFSDETIEW {
_AFSDETIEW { w: self }
}
@@ -357450,8 +356747,7 @@ pub mod sai {
pub fn lfsdet(&mut self) -> _LFSDETW {
_LFSDETW { w: self }
}
- #[doc = "Bit 5 - Clear anticipated frame synchronization detection flag"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Clear anticipated frame synchronization detection flag" ] # [ inline ( always ) ]
pub fn cafsdet(&mut self) -> _CAFSDETW {
_CAFSDETW { w: self }
}
@@ -359696,8 +358992,7 @@ pub mod sai {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bit 6 - Late frame synchronization detection interrupt enable"]
- #[inline(always)]
+ # [ doc = "Bit 6 - Late frame synchronization detection interrupt enable" ] # [ inline ( always ) ]
pub fn lfsdet(&self) -> LFSDETR {
let bits = {
const MASK: bool = true;
@@ -359706,8 +359001,7 @@ pub mod sai {
};
LFSDETR { bits }
}
- #[doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable" ] # [ inline ( always ) ]
pub fn afsdetie(&self) -> AFSDETIER {
let bits = {
const MASK: bool = true;
@@ -359779,13 +359073,11 @@ pub mod sai {
self.bits = bits;
self
}
- #[doc = "Bit 6 - Late frame synchronization detection interrupt enable"]
- #[inline(always)]
+ # [ doc = "Bit 6 - Late frame synchronization detection interrupt enable" ] # [ inline ( always ) ]
pub fn lfsdet(&mut self) -> _LFSDETW {
_LFSDETW { w: self }
}
- #[doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable"]
- #[inline(always)]
+ # [ doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable" ] # [ inline ( always ) ]
pub fn afsdetie(&mut self) -> _AFSDETIEW {
_AFSDETIEW { w: self }
}
@@ -360256,8 +359548,7 @@ pub mod sai {
};
FREQR { bits }
}
- #[doc = "Bit 2 - Wrong clock configuration flag. This bit is read only."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wrong clock configuration flag. This bit is read only." ] # [ inline ( always ) ]
pub fn wckcfg(&self) -> WCKCFGR {
let bits = {
const MASK: bool = true;
@@ -360324,8 +359615,7 @@ pub mod sai {
pub fn freq(&mut self) -> _FREQW {
_FREQW { w: self }
}
- #[doc = "Bit 2 - Wrong clock configuration flag. This bit is read only."]
- #[inline(always)]
+ # [ doc = "Bit 2 - Wrong clock configuration flag. This bit is read only." ] # [ inline ( always ) ]
pub fn wckcfg(&mut self) -> _WCKCFGW {
_WCKCFGW { w: self }
}
@@ -360671,8 +359961,7 @@ pub mod sai {
};
LFSDETR { bits }
}
- #[doc = "Bit 5 - Clear anticipated frame synchronization detection flag."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Clear anticipated frame synchronization detection flag." ] # [ inline ( always ) ]
pub fn cafsdet(&self) -> CAFSDETR {
let bits = {
const MASK: bool = true;
@@ -360739,8 +360028,7 @@ pub mod sai {
pub fn lfsdet(&mut self) -> _LFSDETW {
_LFSDETW { w: self }
}
- #[doc = "Bit 5 - Clear anticipated frame synchronization detection flag."]
- #[inline(always)]
+ # [ doc = "Bit 5 - Clear anticipated frame synchronization detection flag." ] # [ inline ( always ) ]
pub fn cafsdet(&mut self) -> _CAFSDETW {
_CAFSDETW { w: self }
}
@@ -362337,8 +361625,7 @@ pub mod aes {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - initialization vector register (LSB IVR [31:0])"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - initialization vector register (LSB IVR [31:0])" ] # [ inline ( always ) ]
pub fn aes_ivr0(&self) -> AES_IVR0R {
let bits = {
const MASK: u32 = 4294967295;
@@ -362360,8 +361647,7 @@ pub mod aes {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - initialization vector register (LSB IVR [31:0])"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - initialization vector register (LSB IVR [31:0])" ] # [ inline ( always ) ]
pub fn aes_ivr0(&mut self) -> _AES_IVR0W {
_AES_IVR0W { w: self }
}
@@ -362673,8 +361959,7 @@ pub mod aes {
pub fn bits(&self) -> u32 {
self.bits
}
- #[doc = "Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])" ] # [ inline ( always ) ]
pub fn aes_ivr3(&self) -> AES_IVR3R {
let bits = {
const MASK: u32 = 4294967295;
@@ -362696,8 +361981,7 @@ pub mod aes {
self.bits = bits;
self
}
- #[doc = "Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])"]
- #[inline(always)]
+ # [ doc = "Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])" ] # [ inline ( always ) ]
pub fn aes_ivr3(&mut self) -> _AES_IVR3W {
_AES_IVR3W { w: self }
}