From 7ff08a56b37a1ba9845a95a9a3c863f7e80ed963 Mon Sep 17 00:00:00 2001
From: Per Lindgren <per.lindgren@ltu.se>
Date: Sat, 13 Oct 2018 19:19:24 +0200
Subject: [PATCH] svd2rust-v0.12.0

---
 src/lib.rs | 1681 +++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 1278 insertions(+), 403 deletions(-)

diff --git a/src/lib.rs b/src/lib.rs
index 1557581..4cd362a 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,12 +1,21 @@
-# ! [ cfg_attr ( feature = "rt" , feature ( global_asm ) ) ] # ! [ cfg_attr ( feature = "rt" , feature ( macro_reexport ) ) ] # ! [ cfg_attr ( feature = "rt" , feature ( used ) ) ] # ! [ doc = "Peripheral access API for STM32F413 microcontrollers (generated using svd2rust v0.12.0)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.12.0/svd2rust/#peripheral-api" ] # ! [ allow ( private_no_mangle_statics ) ] # ! [ deny ( missing_docs ) ] # ! [ deny ( warnings ) ] # ! [ allow ( non_camel_case_types ) ] # ! [ feature ( const_fn ) ] # ! [ no_std ]
+#![cfg_attr(feature = "rt", feature(global_asm))]
+#![cfg_attr(feature = "rt", feature(macro_reexport))]
+#![cfg_attr(feature = "rt", feature(used))]
+#![doc = "Peripheral access API for STM32F413 microcontrollers (generated using svd2rust v0.12.0)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.12.0/svd2rust/#peripheral-api"]
+#![allow(private_no_mangle_statics)]
+#![deny(missing_docs)]
+#![deny(warnings)]
+#![allow(non_camel_case_types)]
+#![feature(const_fn)]
+#![no_std]
 extern crate bare_metal;
 extern crate cortex_m;
 #[macro_reexport(default_handler, exception)]
 #[cfg(feature = "rt")]
 extern crate cortex_m_rt;
 extern crate vcell;
-use core::ops::Deref;
 use core::marker::PhantomData;
+use core::ops::Deref;
 #[doc = r" Number available in the NVIC for configuring priority"]
 pub const NVIC_PRIO_BITS: u8 = 4;
 pub use interrupt::Interrupt;
@@ -130,7 +139,7 @@ pub mod interrupt {
         fn DFSDM2_FILTER3();
         fn DFSDM2_FILTER4();
     }
-    #[allow(private_no_mangle_statics)]
+    //#[allow(private_no_mangle_statics)]
     #[cfg(feature = "rt")]
     #[doc(hidden)]
     #[link_section = ".vector_table.interrupts"]
@@ -241,7 +250,200 @@ pub mod interrupt {
         Some(DFSDM2_FILTER4),
     ];
     #[doc = r" Enumeration of all the interrupts"]
-    pub enum Interrupt {# [ doc = "0 - Window Watchdog interrupt" ] WWDG , # [ doc = "1 - PVD through EXTI line detection interrupt" ] PVD , # [ doc = "2 - Tamper and TimeStamp interrupts through the EXTI line" ] TAMP_STAMP , # [ doc = "3 - RTC Wakeup interrupt through the EXTI line" ] RTC_WKUP , # [ doc = "4 - FLASH global interrupt" ] FLASH , # [ doc = "5 - RCC global interrupt" ] RCC , # [ doc = "6 - EXTI Line0 interrupt" ] EXTI0 , # [ doc = "7 - EXTI Line1 interrupt" ] EXTI1 , # [ doc = "8 - EXTI Line2 interrupt" ] EXTI2 , # [ doc = "9 - EXTI Line3 interrupt" ] EXTI3 , # [ doc = "10 - EXTI Line4 interrupt" ] EXTI4 , # [ doc = "11 - DMA1 Stream0 global interrupt" ] DMA1_STREAM0 , # [ doc = "12 - DMA1 Stream1 global interrupt" ] DMA1_STREAM1 , # [ doc = "13 - DMA1 Stream2 global interrupt" ] DMA1_STREAM2 , # [ doc = "14 - DMA1 Stream3 global interrupt" ] DMA1_STREAM3 , # [ doc = "15 - DMA1 Stream4 global interrupt" ] DMA1_STREAM4 , # [ doc = "16 - DMA1 Stream5 global interrupt" ] DMA1_STREAM5 , # [ doc = "17 - DMA1 Stream6 global interrupt" ] DMA1_STREAM6 , # [ doc = "18 - ADC1 global interrupt" ] ADC , # [ doc = "19 - CAN1 TX interrupts" ] CAN1_TX , # [ doc = "20 - CAN1 RX0 interrupts" ] CAN1_RX0 , # [ doc = "21 - CAN1 RX1 interrupts" ] CAN1_RX1 , # [ doc = "22 - CAN1 SCE interrupt" ] CAN1_SCE , # [ doc = "23 - EXTI Line[9:5] interrupts" ] EXTI9_5 , # [ doc = "24 - TIM1 Break interrupt and TIM9 global interrupt" ] TIM1_BRK_TIM9 , # [ doc = "25 - TIM1 Update interrupt and TIM10 global interrupt" ] TIM1_UP_TIM10 , # [ doc = "26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt" ] TIM1_TRG_COM_TIM11 , # [ doc = "27 - TIM1 Capture Compare interrupt" ] TIM1_CC , # [ doc = "28 - TIM2 global interrupt" ] TIM2 , # [ doc = "29 - TIM3 global interrupt" ] TIM3 , # [ doc = "30 - TIM4 global interrupt" ] TIM4 , # [ doc = "31 - I2C1 event interrupt" ] I2C1_EVT , # [ doc = "32 - I2C1 error interrupt" ] I2C1_ERR , # [ doc = "33 - I2C2 event interrupt" ] I2C2_EVT , # [ doc = "34 - I2C2 error interrupt" ] I2C2_ERR , # [ doc = "35 - SPI1 global interrupt" ] SPI1 , # [ doc = "36 - SPI2 global interrupt" ] SPI2 , # [ doc = "37 - USART1 global interrupt" ] USART1 , # [ doc = "38 - USART2 global interrupt" ] USART2 , # [ doc = "39 - USART3 global interrupt" ] USART3 , # [ doc = "40 - EXTI Line[15:10] interrupts" ] EXTI15_10 , # [ doc = "41 - RTC Alarms (A and B) through EXTI line interrupt" ] EXTI17_RTC_ALARM , # [ doc = "42 - USB On-The-Go FS Wakeup through EXTI line interrupt" ] EXTI18_OTG_FS_WKUP , # [ doc = "43 - Timer 12 global interrupt" ] TIM8_BRK_TIM12 , # [ doc = "44 - Timer 13 global interrupt" ] TIM8_UP_TIM13 , # [ doc = "45 - Timer 14 global interrupt" ] TIM8_TRG_COM_TIM14 , # [ doc = "46 - TIM8 Cap/Com interrupt" ] TIM8_CC , # [ doc = "47 - DMA1 global interrupt Channel 7" ] DMA1_STREAM7 , # [ doc = "48 - FSMC global interrupt" ] FSMC , # [ doc = "49 - SDIO global interrupt" ] SDIO , # [ doc = "50 - TIM5 global interrupt" ] TIM5 , # [ doc = "51 - SPI3 global interrupt" ] SPI3 , # [ doc = "52 - UART 4 global interrupt" ] USART4 , # [ doc = "53 - UART 5global interrupt" ] UART5 , # [ doc = "54 - TIM6 global and DAC12 underrun interrupts" ] TIM6_GLB_IT_DAC1_DAC2 , # [ doc = "55 - TIM7 global interrupt" ] TIM7 , # [ doc = "56 - DMA2 Stream0 global interrupt" ] DMA2_STREAM0 , # [ doc = "57 - DMA2 Stream1 global interrupt" ] DMA2_STREAM1 , # [ doc = "58 - DMA2 Stream2 global interrupt" ] DMA2_STREAM2 , # [ doc = "59 - DMA2 Stream3 global interrupt" ] DMA2_STREAM3 , # [ doc = "60 - DMA2 Stream4 global interrupt" ] DMA2_STREAM4 , # [ doc = "61 - SD filter0 global interrupt" ] DFSDM1_FLT0 , # [ doc = "62 - SD filter1 global interrupt" ] DFSDM1_FLT1 , # [ doc = "63 - CAN2 TX interrupt" ] CAN2_TX , # [ doc = "64 - BXCAN2 RX0 interrupt" ] CAN2_RX0 , # [ doc = "65 - BXCAN2 RX1 interrupt" ] CAN2_RX1 , # [ doc = "66 - CAN2 SCE interrupt" ] CAN2_SCE , # [ doc = "67 - USB On The Go FS global interrupt" ] OTG_FS_USB , # [ doc = "68 - DMA2 Stream5 global interrupt" ] DMA2_STREAM5 , # [ doc = "69 - DMA2 Stream6 global interrupt" ] DMA2_STREAM6 , # [ doc = "70 - DMA2 Stream7 global interrupt" ] DMA2_STREAM7 , # [ doc = "71 - USART6 global interrupt" ] USART6 , # [ doc = "72 - I2C3 event interrupt" ] I2C3_EV , # [ doc = "73 - I2C3 error interrupt" ] I2C3_ER , # [ doc = "74 - CAN 3 TX interrupt" ] CAN3_TX , # [ doc = "75 - BxCAN 3 RX0 interrupt" ] CAN3_RX0 , # [ doc = "76 - BxCAN 3 RX1 interrupt" ] CAN3_RX1 , # [ doc = "77 - CAN 3 SCE interrupt" ] CAN3_SCE , # [ doc = "79 - AES global interrupt" ] CRYPTO , # [ doc = "80 - Rng global interrupt" ] RNG , # [ doc = "81 - FPU global interrupt" ] FPU , # [ doc = "82 - USART7 global interrupt" ] USART7 , # [ doc = "83 - USART8 global interrupt" ] USART8 , # [ doc = "84 - SPI4 global interrupt" ] SPI4 , # [ doc = "85 - SPI5 global interrupt" ] SPI5 , # [ doc = "87 - SAI1 global interrupt" ] SAI1 , # [ doc = "88 - UART9 global interrupt" ] UART9 , # [ doc = "89 - UART10 global interrupt" ] UART10 , # [ doc = "92 - Quad-SPI global interrupt" ] QUADSPI , # [ doc = "95 - I2CFMP1 event interrupt" ] I2CFMP1EVENT , # [ doc = "96 - I2CFMP1 error interrupt" ] I2CFMP1ERROR , # [ doc = "97 - LP Timer global interrupt or EXT1 interrupt line 23" ] LPTIM1_OR_IT_EIT_23 , # [ doc = "98 - DFSDM2 SD filter 1 global interrupt" ] DFSDM2_FILTER1 , # [ doc = "99 - DFSDM2 SD filter 2 global interrupt" ] DFSDM2_FILTER2 , # [ doc = "100 - DFSDM2 SD filter 3 global interrupt" ] DFSDM2_FILTER3 , # [ doc = "101 - DFSDM2 SD filter 4 global interrupt" ] DFSDM2_FILTER4 ,}
+    pub enum Interrupt {
+        #[doc = "0 - Window Watchdog interrupt"]
+        WWDG,
+        #[doc = "1 - PVD through EXTI line detection interrupt"]
+        PVD,
+        #[doc = "2 - Tamper and TimeStamp interrupts through the EXTI line"]
+        TAMP_STAMP,
+        #[doc = "3 - RTC Wakeup interrupt through the EXTI line"]
+        RTC_WKUP,
+        #[doc = "4 - FLASH global interrupt"]
+        FLASH,
+        #[doc = "5 - RCC global interrupt"]
+        RCC,
+        #[doc = "6 - EXTI Line0 interrupt"]
+        EXTI0,
+        #[doc = "7 - EXTI Line1 interrupt"]
+        EXTI1,
+        #[doc = "8 - EXTI Line2 interrupt"]
+        EXTI2,
+        #[doc = "9 - EXTI Line3 interrupt"]
+        EXTI3,
+        #[doc = "10 - EXTI Line4 interrupt"]
+        EXTI4,
+        #[doc = "11 - DMA1 Stream0 global interrupt"]
+        DMA1_STREAM0,
+        #[doc = "12 - DMA1 Stream1 global interrupt"]
+        DMA1_STREAM1,
+        #[doc = "13 - DMA1 Stream2 global interrupt"]
+        DMA1_STREAM2,
+        #[doc = "14 - DMA1 Stream3 global interrupt"]
+        DMA1_STREAM3,
+        #[doc = "15 - DMA1 Stream4 global interrupt"]
+        DMA1_STREAM4,
+        #[doc = "16 - DMA1 Stream5 global interrupt"]
+        DMA1_STREAM5,
+        #[doc = "17 - DMA1 Stream6 global interrupt"]
+        DMA1_STREAM6,
+        #[doc = "18 - ADC1 global interrupt"]
+        ADC,
+        #[doc = "19 - CAN1 TX interrupts"]
+        CAN1_TX,
+        #[doc = "20 - CAN1 RX0 interrupts"]
+        CAN1_RX0,
+        #[doc = "21 - CAN1 RX1 interrupts"]
+        CAN1_RX1,
+        #[doc = "22 - CAN1 SCE interrupt"]
+        CAN1_SCE,
+        #[doc = "23 - EXTI Line[9:5] interrupts"]
+        EXTI9_5,
+        #[doc = "24 - TIM1 Break interrupt and TIM9 global interrupt"]
+        TIM1_BRK_TIM9,
+        #[doc = "25 - TIM1 Update interrupt and TIM10 global interrupt"]
+        TIM1_UP_TIM10,
+        #[doc = "26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt"]
+        TIM1_TRG_COM_TIM11,
+        #[doc = "27 - TIM1 Capture Compare interrupt"]
+        TIM1_CC,
+        #[doc = "28 - TIM2 global interrupt"]
+        TIM2,
+        #[doc = "29 - TIM3 global interrupt"]
+        TIM3,
+        #[doc = "30 - TIM4 global interrupt"]
+        TIM4,
+        #[doc = "31 - I2C1 event interrupt"]
+        I2C1_EVT,
+        #[doc = "32 - I2C1 error interrupt"]
+        I2C1_ERR,
+        #[doc = "33 - I2C2 event interrupt"]
+        I2C2_EVT,
+        #[doc = "34 - I2C2 error interrupt"]
+        I2C2_ERR,
+        #[doc = "35 - SPI1 global interrupt"]
+        SPI1,
+        #[doc = "36 - SPI2 global interrupt"]
+        SPI2,
+        #[doc = "37 - USART1 global interrupt"]
+        USART1,
+        #[doc = "38 - USART2 global interrupt"]
+        USART2,
+        #[doc = "39 - USART3 global interrupt"]
+        USART3,
+        #[doc = "40 - EXTI Line[15:10] interrupts"]
+        EXTI15_10,
+        #[doc = "41 - RTC Alarms (A and B) through EXTI line interrupt"]
+        EXTI17_RTC_ALARM,
+        #[doc = "42 - USB On-The-Go FS Wakeup through EXTI line interrupt"]
+        EXTI18_OTG_FS_WKUP,
+        #[doc = "43 - Timer 12 global interrupt"]
+        TIM8_BRK_TIM12,
+        #[doc = "44 - Timer 13 global interrupt"]
+        TIM8_UP_TIM13,
+        #[doc = "45 - Timer 14 global interrupt"]
+        TIM8_TRG_COM_TIM14,
+        #[doc = "46 - TIM8 Cap/Com interrupt"]
+        TIM8_CC,
+        #[doc = "47 - DMA1 global interrupt Channel 7"]
+        DMA1_STREAM7,
+        #[doc = "48 - FSMC global interrupt"]
+        FSMC,
+        #[doc = "49 - SDIO global interrupt"]
+        SDIO,
+        #[doc = "50 - TIM5 global interrupt"]
+        TIM5,
+        #[doc = "51 - SPI3 global interrupt"]
+        SPI3,
+        #[doc = "52 - UART 4 global interrupt"]
+        USART4,
+        #[doc = "53 - UART 5global interrupt"]
+        UART5,
+        #[doc = "54 - TIM6 global and DAC12 underrun interrupts"]
+        TIM6_GLB_IT_DAC1_DAC2,
+        #[doc = "55 - TIM7 global interrupt"]
+        TIM7,
+        #[doc = "56 - DMA2 Stream0 global interrupt"]
+        DMA2_STREAM0,
+        #[doc = "57 - DMA2 Stream1 global interrupt"]
+        DMA2_STREAM1,
+        #[doc = "58 - DMA2 Stream2 global interrupt"]
+        DMA2_STREAM2,
+        #[doc = "59 - DMA2 Stream3 global interrupt"]
+        DMA2_STREAM3,
+        #[doc = "60 - DMA2 Stream4 global interrupt"]
+        DMA2_STREAM4,
+        #[doc = "61 - SD filter0 global interrupt"]
+        DFSDM1_FLT0,
+        #[doc = "62 - SD filter1 global interrupt"]
+        DFSDM1_FLT1,
+        #[doc = "63 - CAN2 TX interrupt"]
+        CAN2_TX,
+        #[doc = "64 - BXCAN2 RX0 interrupt"]
+        CAN2_RX0,
+        #[doc = "65 - BXCAN2 RX1 interrupt"]
+        CAN2_RX1,
+        #[doc = "66 - CAN2 SCE interrupt"]
+        CAN2_SCE,
+        #[doc = "67 - USB On The Go FS global interrupt"]
+        OTG_FS_USB,
+        #[doc = "68 - DMA2 Stream5 global interrupt"]
+        DMA2_STREAM5,
+        #[doc = "69 - DMA2 Stream6 global interrupt"]
+        DMA2_STREAM6,
+        #[doc = "70 - DMA2 Stream7 global interrupt"]
+        DMA2_STREAM7,
+        #[doc = "71 - USART6 global interrupt"]
+        USART6,
+        #[doc = "72 - I2C3 event interrupt"]
+        I2C3_EV,
+        #[doc = "73 - I2C3 error interrupt"]
+        I2C3_ER,
+        #[doc = "74 - CAN 3 TX interrupt"]
+        CAN3_TX,
+        #[doc = "75 - BxCAN 3 RX0 interrupt"]
+        CAN3_RX0,
+        #[doc = "76 - BxCAN 3 RX1 interrupt"]
+        CAN3_RX1,
+        #[doc = "77 - CAN 3 SCE interrupt"]
+        CAN3_SCE,
+        #[doc = "79 - AES global interrupt"]
+        CRYPTO,
+        #[doc = "80 - Rng global interrupt"]
+        RNG,
+        #[doc = "81 - FPU global interrupt"]
+        FPU,
+        #[doc = "82 - USART7 global interrupt"]
+        USART7,
+        #[doc = "83 - USART8 global interrupt"]
+        USART8,
+        #[doc = "84 - SPI4 global interrupt"]
+        SPI4,
+        #[doc = "85 - SPI5 global interrupt"]
+        SPI5,
+        #[doc = "87 - SAI1 global interrupt"]
+        SAI1,
+        #[doc = "88 - UART9 global interrupt"]
+        UART9,
+        #[doc = "89 - UART10 global interrupt"]
+        UART10,
+        #[doc = "92 - Quad-SPI global interrupt"]
+        QUADSPI,
+        #[doc = "95 - I2CFMP1 event interrupt"]
+        I2CFMP1EVENT,
+        #[doc = "96 - I2CFMP1 error interrupt"]
+        I2CFMP1ERROR,
+        #[doc = "97 - LP Timer global interrupt or EXT1 interrupt line 23"]
+        LPTIM1_OR_IT_EIT_23,
+        #[doc = "98 - DFSDM2 SD filter 1 global interrupt"]
+        DFSDM2_FILTER1,
+        #[doc = "99 - DFSDM2 SD filter 2 global interrupt"]
+        DFSDM2_FILTER2,
+        #[doc = "100 - DFSDM2 SD filter 3 global interrupt"]
+        DFSDM2_FILTER3,
+        #[doc = "101 - DFSDM2 SD filter 4 global interrupt"]
+        DFSDM2_FILTER4,
+    }
     unsafe impl Nr for Interrupt {
         #[inline]
         fn nr(&self) -> u8 {
@@ -1549,7 +1751,8 @@ pub mod adc1 {
                 };
                 JAUTOR { bits }
             }
-            # [ doc = "Bit 9 - Enable the watchdog on a single channel in scan mode" ] # [ inline ]
+            #[doc = "Bit 9 - Enable the watchdog on a single channel in scan mode"]
+            #[inline]
             pub fn awdsgl(&self) -> AWDSGLR {
                 let bits = {
                     const MASK: bool = true;
@@ -1661,7 +1864,8 @@ pub mod adc1 {
             pub fn jauto(&mut self) -> _JAUTOW {
                 _JAUTOW { w: self }
             }
-            # [ doc = "Bit 9 - Enable the watchdog on a single channel in scan mode" ] # [ inline ]
+            #[doc = "Bit 9 - Enable the watchdog on a single channel in scan mode"]
+            #[inline]
             pub fn awdsgl(&mut self) -> _AWDSGLW {
                 _AWDSGLW { w: self }
             }
@@ -6791,16 +6995,12 @@ pub mod dbg {
             }
             #[doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"]
             #[inline]
-            pub fn dbg_i2c1_smbus_timeout(
-                &mut self,
-            ) -> _DBG_I2C1_SMBUS_TIMEOUTW {
+            pub fn dbg_i2c1_smbus_timeout(&mut self) -> _DBG_I2C1_SMBUS_TIMEOUTW {
                 _DBG_I2C1_SMBUS_TIMEOUTW { w: self }
             }
             #[doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"]
             #[inline]
-            pub fn dbg_i2c2_smbus_timeout(
-                &mut self,
-            ) -> _DBG_I2C2_SMBUS_TIMEOUTW {
+            pub fn dbg_i2c2_smbus_timeout(&mut self) -> _DBG_I2C2_SMBUS_TIMEOUTW {
                 _DBG_I2C2_SMBUS_TIMEOUTW { w: self }
             }
             #[doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"]
@@ -19146,7 +19346,8 @@ pub mod pwr {
                 };
                 BRER { bits }
             }
-            # [ doc = "Bit 14 - Regulator voltage scaling output selection ready bit" ] # [ inline ]
+            #[doc = "Bit 14 - Regulator voltage scaling output selection ready bit"]
+            #[inline]
             pub fn vosrdy(&self) -> VOSRDYR {
                 let bits = {
                     const MASK: bool = true;
@@ -19178,7 +19379,8 @@ pub mod pwr {
             pub fn bre(&mut self) -> _BREW {
                 _BREW { w: self }
             }
-            # [ doc = "Bit 14 - Regulator voltage scaling output selection ready bit" ] # [ inline ]
+            #[doc = "Bit 14 - Regulator voltage scaling output selection ready bit"]
+            #[inline]
             pub fn vosrdy(&mut self) -> _VOSRDYW {
                 _VOSRDYW { w: self }
             }
@@ -19207,7 +19409,68 @@ pub mod rcc {
     use vcell::VolatileCell;
     #[doc = r" Register block"]
     #[repr(C)]
-    pub struct RegisterBlock { # [ doc = "0x00 - clock control register" ] pub cr : CR , # [ doc = "0x04 - PLL configuration register" ] pub pllcfgr : PLLCFGR , # [ doc = "0x08 - clock configuration register" ] pub cfgr : CFGR , # [ doc = "0x0c - clock interrupt register" ] pub cir : CIR , # [ doc = "0x10 - AHB1 peripheral reset register" ] pub ahb1rstr : AHB1RSTR , # [ doc = "0x14 - AHB2 peripheral reset register" ] pub ahb2rstr : AHB2RSTR , # [ doc = "0x18 - peripheral reset register" ] pub ahb3rstr : AHB3RSTR , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x20 - APB1 peripheral reset register" ] pub apb1rstr : APB1RSTR , # [ doc = "0x24 - APB2 peripheral reset register" ] pub apb2rstr : APB2RSTR , _reserved1 : [ u8 ; 8usize ] , # [ doc = "0x30 - AHB1 peripheral clock register" ] pub ahb1enr : AHB1ENR , # [ doc = "0x34 - AHB2 peripheral clock enable register" ] pub ahb2enr : AHB2ENR , # [ doc = "0x38 - AHB3 peripheral clock enable register" ] pub ahb3enr : AHB3ENR , _reserved2 : [ u8 ; 4usize ] , # [ doc = "0x40 - APB1 peripheral clock enable register" ] pub apb1enr : APB1ENR , # [ doc = "0x44 - APB2 peripheral clock enable register" ] pub apb2enr : APB2ENR , _reserved3 : [ u8 ; 8usize ] , # [ doc = "0x50 - AHB1 peripheral clock enable in low power mode register" ] pub ahb1lpenr : AHB1LPENR , # [ doc = "0x54 - AHB2 peripheral clock enable in low power mode register" ] pub ahb2lpenr : AHB2LPENR , # [ doc = "0x58 - AHB3 peripheral clock enable in low power mode register" ] pub ahb3lpenr : AHB3LPENR , _reserved4 : [ u8 ; 4usize ] , # [ doc = "0x60 - APB1 peripheral clock enable in low power mode register" ] pub apb1lpenr : APB1LPENR , # [ doc = "0x64 - APB2 peripheral clock enabled in low power mode register" ] pub apb2lpenr : APB2LPENR , _reserved5 : [ u8 ; 8usize ] , # [ doc = "0x70 - Backup domain control register" ] pub bdcr : BDCR , # [ doc = "0x74 - clock control & status register" ] pub csr : CSR , _reserved6 : [ u8 ; 8usize ] , # [ doc = "0x80 - spread spectrum clock generation register" ] pub sscgr : SSCGR , # [ doc = "0x84 - PLLI2S configuration register" ] pub plli2scfgr : PLLI2SCFGR , _reserved7 : [ u8 ; 4usize ] , # [ doc = "0x8c - Dedicated Clocks Configuration Register" ] pub dckcfgr : DCKCFGR , # [ doc = "0x90 - RCC clocks gated enable register" ] pub ckgatenr : CKGATENR , # [ doc = "0x94 - Dedicated Clocks Configuration Register" ] pub dckcfgr2 : DCKCFGR2 , }
+    pub struct RegisterBlock {
+        #[doc = "0x00 - clock control register"]
+        pub cr: CR,
+        #[doc = "0x04 - PLL configuration register"]
+        pub pllcfgr: PLLCFGR,
+        #[doc = "0x08 - clock configuration register"]
+        pub cfgr: CFGR,
+        #[doc = "0x0c - clock interrupt register"]
+        pub cir: CIR,
+        #[doc = "0x10 - AHB1 peripheral reset register"]
+        pub ahb1rstr: AHB1RSTR,
+        #[doc = "0x14 - AHB2 peripheral reset register"]
+        pub ahb2rstr: AHB2RSTR,
+        #[doc = "0x18 - peripheral reset register"]
+        pub ahb3rstr: AHB3RSTR,
+        _reserved0: [u8; 4usize],
+        #[doc = "0x20 - APB1 peripheral reset register"]
+        pub apb1rstr: APB1RSTR,
+        #[doc = "0x24 - APB2 peripheral reset register"]
+        pub apb2rstr: APB2RSTR,
+        _reserved1: [u8; 8usize],
+        #[doc = "0x30 - AHB1 peripheral clock register"]
+        pub ahb1enr: AHB1ENR,
+        #[doc = "0x34 - AHB2 peripheral clock enable register"]
+        pub ahb2enr: AHB2ENR,
+        #[doc = "0x38 - AHB3 peripheral clock enable register"]
+        pub ahb3enr: AHB3ENR,
+        _reserved2: [u8; 4usize],
+        #[doc = "0x40 - APB1 peripheral clock enable register"]
+        pub apb1enr: APB1ENR,
+        #[doc = "0x44 - APB2 peripheral clock enable register"]
+        pub apb2enr: APB2ENR,
+        _reserved3: [u8; 8usize],
+        #[doc = "0x50 - AHB1 peripheral clock enable in low power mode register"]
+        pub ahb1lpenr: AHB1LPENR,
+        #[doc = "0x54 - AHB2 peripheral clock enable in low power mode register"]
+        pub ahb2lpenr: AHB2LPENR,
+        #[doc = "0x58 - AHB3 peripheral clock enable in low power mode register"]
+        pub ahb3lpenr: AHB3LPENR,
+        _reserved4: [u8; 4usize],
+        #[doc = "0x60 - APB1 peripheral clock enable in low power mode register"]
+        pub apb1lpenr: APB1LPENR,
+        #[doc = "0x64 - APB2 peripheral clock enabled in low power mode register"]
+        pub apb2lpenr: APB2LPENR,
+        _reserved5: [u8; 8usize],
+        #[doc = "0x70 - Backup domain control register"]
+        pub bdcr: BDCR,
+        #[doc = "0x74 - clock control & status register"]
+        pub csr: CSR,
+        _reserved6: [u8; 8usize],
+        #[doc = "0x80 - spread spectrum clock generation register"]
+        pub sscgr: SSCGR,
+        #[doc = "0x84 - PLLI2S configuration register"]
+        pub plli2scfgr: PLLI2SCFGR,
+        _reserved7: [u8; 4usize],
+        #[doc = "0x8c - Dedicated Clocks Configuration Register"]
+        pub dckcfgr: DCKCFGR,
+        #[doc = "0x90 - RCC clocks gated enable register"]
+        pub ckgatenr: CKGATENR,
+        #[doc = "0x94 - Dedicated Clocks Configuration Register"]
+        pub dckcfgr2: DCKCFGR2,
+    }
     #[doc = "clock control register"]
     pub struct CR {
         register: VolatileCell<u32>,
@@ -21001,7 +21264,8 @@ pub mod rcc {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bit 27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" ] # [ inline ]
+            #[doc = "Bit 27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"]
+            #[inline]
             pub fn pllq3(&self) -> PLLQ3R {
                 let bits = {
                     const MASK: bool = true;
@@ -21010,7 +21274,8 @@ pub mod rcc {
                 };
                 PLLQ3R { bits }
             }
-            # [ doc = "Bit 26 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" ] # [ inline ]
+            #[doc = "Bit 26 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"]
+            #[inline]
             pub fn pllq2(&self) -> PLLQ2R {
                 let bits = {
                     const MASK: bool = true;
@@ -21019,7 +21284,8 @@ pub mod rcc {
                 };
                 PLLQ2R { bits }
             }
-            # [ doc = "Bit 25 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" ] # [ inline ]
+            #[doc = "Bit 25 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"]
+            #[inline]
             pub fn pllq1(&self) -> PLLQ1R {
                 let bits = {
                     const MASK: bool = true;
@@ -21028,7 +21294,8 @@ pub mod rcc {
                 };
                 PLLQ1R { bits }
             }
-            # [ doc = "Bit 24 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" ] # [ inline ]
+            #[doc = "Bit 24 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"]
+            #[inline]
             pub fn pllq0(&self) -> PLLQ0R {
                 let bits = {
                     const MASK: bool = true;
@@ -21037,7 +21304,8 @@ pub mod rcc {
                 };
                 PLLQ0R { bits }
             }
-            # [ doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source" ] # [ inline ]
+            #[doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"]
+            #[inline]
             pub fn pllsrc(&self) -> PLLSRCR {
                 let bits = {
                     const MASK: bool = true;
@@ -21046,7 +21314,8 @@ pub mod rcc {
                 };
                 PLLSRCR { bits }
             }
-            # [ doc = "Bit 17 - Main PLL (PLL) division factor for main system clock" ] # [ inline ]
+            #[doc = "Bit 17 - Main PLL (PLL) division factor for main system clock"]
+            #[inline]
             pub fn pllp1(&self) -> PLLP1R {
                 let bits = {
                     const MASK: bool = true;
@@ -21055,7 +21324,8 @@ pub mod rcc {
                 };
                 PLLP1R { bits }
             }
-            # [ doc = "Bit 16 - Main PLL (PLL) division factor for main system clock" ] # [ inline ]
+            #[doc = "Bit 16 - Main PLL (PLL) division factor for main system clock"]
+            #[inline]
             pub fn pllp0(&self) -> PLLP0R {
                 let bits = {
                     const MASK: bool = true;
@@ -21154,7 +21424,8 @@ pub mod rcc {
                 };
                 PLLN0R { bits }
             }
-            # [ doc = "Bit 5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm5(&self) -> PLLM5R {
                 let bits = {
                     const MASK: bool = true;
@@ -21163,7 +21434,8 @@ pub mod rcc {
                 };
                 PLLM5R { bits }
             }
-            # [ doc = "Bit 4 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 4 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm4(&self) -> PLLM4R {
                 let bits = {
                     const MASK: bool = true;
@@ -21172,7 +21444,8 @@ pub mod rcc {
                 };
                 PLLM4R { bits }
             }
-            # [ doc = "Bit 3 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 3 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm3(&self) -> PLLM3R {
                 let bits = {
                     const MASK: bool = true;
@@ -21181,7 +21454,8 @@ pub mod rcc {
                 };
                 PLLM3R { bits }
             }
-            # [ doc = "Bit 2 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 2 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm2(&self) -> PLLM2R {
                 let bits = {
                     const MASK: bool = true;
@@ -21190,7 +21464,8 @@ pub mod rcc {
                 };
                 PLLM2R { bits }
             }
-            # [ doc = "Bit 1 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 1 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm1(&self) -> PLLM1R {
                 let bits = {
                     const MASK: bool = true;
@@ -21199,7 +21474,8 @@ pub mod rcc {
                 };
                 PLLM1R { bits }
             }
-            # [ doc = "Bit 0 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 0 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm0(&self) -> PLLM0R {
                 let bits = {
                     const MASK: bool = true;
@@ -21208,7 +21484,8 @@ pub mod rcc {
                 };
                 PLLM0R { bits }
             }
-            # [ doc = "Bits 28:30 - Main PLL (PLL) division factor for I2S, DFSDM clocks" ] # [ inline ]
+            #[doc = "Bits 28:30 - Main PLL (PLL) division factor for I2S, DFSDM clocks"]
+            #[inline]
             pub fn pllr(&self) -> PLLRR {
                 let bits = {
                     const MASK: u8 = 0x07;
@@ -21230,31 +21507,38 @@ pub mod rcc {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bit 27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" ] # [ inline ]
+            #[doc = "Bit 27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"]
+            #[inline]
             pub fn pllq3(&mut self) -> _PLLQ3W {
                 _PLLQ3W { w: self }
             }
-            # [ doc = "Bit 26 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" ] # [ inline ]
+            #[doc = "Bit 26 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"]
+            #[inline]
             pub fn pllq2(&mut self) -> _PLLQ2W {
                 _PLLQ2W { w: self }
             }
-            # [ doc = "Bit 25 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" ] # [ inline ]
+            #[doc = "Bit 25 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"]
+            #[inline]
             pub fn pllq1(&mut self) -> _PLLQ1W {
                 _PLLQ1W { w: self }
             }
-            # [ doc = "Bit 24 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" ] # [ inline ]
+            #[doc = "Bit 24 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks"]
+            #[inline]
             pub fn pllq0(&mut self) -> _PLLQ0W {
                 _PLLQ0W { w: self }
             }
-            # [ doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source" ] # [ inline ]
+            #[doc = "Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source"]
+            #[inline]
             pub fn pllsrc(&mut self) -> _PLLSRCW {
                 _PLLSRCW { w: self }
             }
-            # [ doc = "Bit 17 - Main PLL (PLL) division factor for main system clock" ] # [ inline ]
+            #[doc = "Bit 17 - Main PLL (PLL) division factor for main system clock"]
+            #[inline]
             pub fn pllp1(&mut self) -> _PLLP1W {
                 _PLLP1W { w: self }
             }
-            # [ doc = "Bit 16 - Main PLL (PLL) division factor for main system clock" ] # [ inline ]
+            #[doc = "Bit 16 - Main PLL (PLL) division factor for main system clock"]
+            #[inline]
             pub fn pllp0(&mut self) -> _PLLP0W {
                 _PLLP0W { w: self }
             }
@@ -21303,31 +21587,38 @@ pub mod rcc {
             pub fn plln0(&mut self) -> _PLLN0W {
                 _PLLN0W { w: self }
             }
-            # [ doc = "Bit 5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm5(&mut self) -> _PLLM5W {
                 _PLLM5W { w: self }
             }
-            # [ doc = "Bit 4 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 4 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm4(&mut self) -> _PLLM4W {
                 _PLLM4W { w: self }
             }
-            # [ doc = "Bit 3 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 3 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm3(&mut self) -> _PLLM3W {
                 _PLLM3W { w: self }
             }
-            # [ doc = "Bit 2 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 2 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm2(&mut self) -> _PLLM2W {
                 _PLLM2W { w: self }
             }
-            # [ doc = "Bit 1 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 1 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm1(&mut self) -> _PLLM1W {
                 _PLLM1W { w: self }
             }
-            # [ doc = "Bit 0 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bit 0 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn pllm0(&mut self) -> _PLLM0W {
                 _PLLM0W { w: self }
             }
-            # [ doc = "Bits 28:30 - Main PLL (PLL) division factor for I2S, DFSDM clocks" ] # [ inline ]
+            #[doc = "Bits 28:30 - Main PLL (PLL) division factor for I2S, DFSDM clocks"]
+            #[inline]
             pub fn pllr(&mut self) -> _PLLRW {
                 _PLLRW { w: self }
             }
@@ -31488,7 +31779,8 @@ pub mod rcc {
                 };
                 RNGLPENR { bits }
             }
-            # [ doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode"]
+            #[inline]
             pub fn fsmclpen(&self) -> FSMCLPENR {
                 let bits = {
                     const MASK: bool = true;
@@ -31497,7 +31789,8 @@ pub mod rcc {
                 };
                 FSMCLPENR { bits }
             }
-            # [ doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode"]
+            #[inline]
             pub fn qspilpen(&self) -> QSPILPENR {
                 let bits = {
                     const MASK: bool = true;
@@ -31529,11 +31822,13 @@ pub mod rcc {
             pub fn rnglpen(&mut self) -> _RNGLPENW {
                 _RNGLPENW { w: self }
             }
-            # [ doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode"]
+            #[inline]
             pub fn fsmclpen(&mut self) -> _FSMCLPENW {
                 _FSMCLPENW { w: self }
             }
-            # [ doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode"]
+            #[inline]
             pub fn qspilpen(&mut self) -> _QSPILPENW {
                 _QSPILPENW { w: self }
             }
@@ -34293,7 +34588,8 @@ pub mod rcc {
                 };
                 SPI4LPENR { bits }
             }
-            # [ doc = "Bit 14 - System configuration controller clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 14 - System configuration controller clock enable during Sleep mode"]
+            #[inline]
             pub fn syscfglpen(&self) -> SYSCFGLPENR {
                 let bits = {
                     const MASK: bool = true;
@@ -34362,7 +34658,8 @@ pub mod rcc {
                 };
                 USART10LPENR { bits }
             }
-            # [ doc = "Bit 15 - EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 15 - EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode"]
+            #[inline]
             pub fn extiten(&self) -> EXTITENR {
                 let bits = {
                     const MASK: bool = true;
@@ -34454,7 +34751,8 @@ pub mod rcc {
             pub fn spi4lpen(&mut self) -> _SPI4LPENW {
                 _SPI4LPENW { w: self }
             }
-            # [ doc = "Bit 14 - System configuration controller clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 14 - System configuration controller clock enable during Sleep mode"]
+            #[inline]
             pub fn syscfglpen(&mut self) -> _SYSCFGLPENW {
                 _SYSCFGLPENW { w: self }
             }
@@ -34488,7 +34786,8 @@ pub mod rcc {
             pub fn usart10lpen(&mut self) -> _USART10LPENW {
                 _USART10LPENW { w: self }
             }
-            # [ doc = "Bit 15 - EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 15 - EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode"]
+            #[inline]
             pub fn extiten(&mut self) -> _EXTITENW {
                 _EXTITENW { w: self }
             }
@@ -36152,7 +36451,8 @@ pub mod rcc {
                 };
                 PLLI2SNR { bits }
             }
-            # [ doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn plli2sm(&self) -> PLLI2SMR {
                 let bits = {
                     const MASK: u8 = 0x3f;
@@ -36171,7 +36471,8 @@ pub mod rcc {
                 };
                 PLLI2SSRCR { bits }
             }
-            # [ doc = "Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock" ] # [ inline ]
+            #[doc = "Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock"]
+            #[inline]
             pub fn plli2sq(&self) -> PLLI2SQR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -36203,7 +36504,8 @@ pub mod rcc {
             pub fn plli2sn(&mut self) -> _PLLI2SNW {
                 _PLLI2SNW { w: self }
             }
-            # [ doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock" ] # [ inline ]
+            #[doc = "Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock"]
+            #[inline]
             pub fn plli2sm(&mut self) -> _PLLI2SMW {
                 _PLLI2SMW { w: self }
             }
@@ -36212,7 +36514,8 @@ pub mod rcc {
             pub fn plli2ssrc(&mut self) -> _PLLI2SSRCW {
                 _PLLI2SSRCW { w: self }
             }
-            # [ doc = "Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock" ] # [ inline ]
+            #[doc = "Bits 24:27 - PLLI2S division factor for USB OTG FS/SDIO/RNG clock"]
+            #[inline]
             pub fn plli2sq(&mut self) -> _PLLI2SQW {
                 _PLLI2SQW { w: self }
             }
@@ -36740,7 +37043,8 @@ pub mod rcc {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode"]
+            #[inline]
             pub fn fsmclpen(&self) -> FSMCLPENR {
                 let bits = {
                     const MASK: bool = true;
@@ -36749,7 +37053,8 @@ pub mod rcc {
                 };
                 FSMCLPENR { bits }
             }
-            # [ doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode"]
+            #[inline]
             pub fn qspilpen(&self) -> QSPILPENR {
                 let bits = {
                     const MASK: bool = true;
@@ -36771,11 +37076,13 @@ pub mod rcc {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 0 - Flexible memory controller module clock enable during Sleep mode"]
+            #[inline]
             pub fn fsmclpen(&mut self) -> _FSMCLPENW {
                 _FSMCLPENW { w: self }
             }
-            # [ doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode" ] # [ inline ]
+            #[doc = "Bit 1 - QUADSPI memory controller module clock enable during Sleep mode"]
+            #[inline]
             pub fn qspilpen(&mut self) -> _QSPILPENW {
                 _QSPILPENW { w: self }
             }
@@ -44546,7 +44853,8 @@ pub mod rtc {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 24:27 - Mask the most-significant bits starting at this bit" ] # [ inline ]
+            #[doc = "Bits 24:27 - Mask the most-significant bits starting at this bit"]
+            #[inline]
             pub fn maskss(&self) -> MASKSSR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -44578,7 +44886,8 @@ pub mod rtc {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 24:27 - Mask the most-significant bits starting at this bit" ] # [ inline ]
+            #[doc = "Bits 24:27 - Mask the most-significant bits starting at this bit"]
+            #[inline]
             pub fn maskss(&mut self) -> _MASKSSW {
                 _MASKSSW { w: self }
             }
@@ -44697,7 +45006,8 @@ pub mod rtc {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 24:27 - Mask the most-significant bits starting at this bit" ] # [ inline ]
+            #[doc = "Bits 24:27 - Mask the most-significant bits starting at this bit"]
+            #[inline]
             pub fn maskss(&self) -> MASKSSR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -44729,7 +45039,8 @@ pub mod rtc {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 24:27 - Mask the most-significant bits starting at this bit" ] # [ inline ]
+            #[doc = "Bits 24:27 - Mask the most-significant bits starting at this bit"]
+            #[inline]
             pub fn maskss(&mut self) -> _MASKSSW {
                 _MASKSSW { w: self }
             }
@@ -48181,7 +48492,8 @@ pub mod sdio {
                 };
                 CPSMENR { bits }
             }
-            # [ doc = "Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)." ] # [ inline ]
+            #[doc = "Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)."]
+            #[inline]
             pub fn waitpend(&self) -> WAITPENDR {
                 let bits = {
                     const MASK: bool = true;
@@ -48258,7 +48570,8 @@ pub mod sdio {
             pub fn cpsmen(&mut self) -> _CPSMENW {
                 _CPSMENW { w: self }
             }
-            # [ doc = "Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)." ] # [ inline ]
+            #[doc = "Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)."]
+            #[inline]
             pub fn waitpend(&mut self) -> _WAITPENDW {
                 _WAITPENDW { w: self }
             }
@@ -49237,7 +49550,8 @@ pub mod sdio {
                 };
                 DMAENR { bits }
             }
-            # [ doc = "Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer." ] # [ inline ]
+            #[doc = "Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer."]
+            #[inline]
             pub fn dtmode(&self) -> DTMODER {
                 let bits = {
                     const MASK: bool = true;
@@ -49309,7 +49623,8 @@ pub mod sdio {
             pub fn dmaen(&mut self) -> _DMAENW {
                 _DMAENW { w: self }
             }
-            # [ doc = "Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer." ] # [ inline ]
+            #[doc = "Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer."]
+            #[inline]
             pub fn dtmode(&mut self) -> _DTMODEW {
                 _DTMODEW { w: self }
             }
@@ -49902,7 +50217,8 @@ pub mod sdio {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bit 23 - CE-ATA command completion signal received for CMD61" ] # [ inline ]
+            #[doc = "Bit 23 - CE-ATA command completion signal received for CMD61"]
+            #[inline]
             pub fn ceataend(&self) -> CEATAENDR {
                 let bits = {
                     const MASK: bool = true;
@@ -49981,7 +50297,8 @@ pub mod sdio {
                 };
                 TXFIFOFR { bits }
             }
-            # [ doc = "Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO" ] # [ inline ]
+            #[doc = "Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO"]
+            #[inline]
             pub fn rxfifohf(&self) -> RXFIFOHFR {
                 let bits = {
                     const MASK: bool = true;
@@ -49990,7 +50307,8 @@ pub mod sdio {
                 };
                 RXFIFOHFR { bits }
             }
-            # [ doc = "Bit 14 - Transmit FIFO half empty: at least 8 words can be written into the FIFO" ] # [ inline ]
+            #[doc = "Bit 14 - Transmit FIFO half empty: at least 8 words can be written into the FIFO"]
+            #[inline]
             pub fn txfifohe(&self) -> TXFIFOHER {
                 let bits = {
                     const MASK: bool = true;
@@ -50039,7 +50357,8 @@ pub mod sdio {
                 };
                 DBCKENDR { bits }
             }
-            # [ doc = "Bit 9 - Start bit not detected on all data signals in wide bus mode" ] # [ inline ]
+            #[doc = "Bit 9 - Start bit not detected on all data signals in wide bus mode"]
+            #[inline]
             pub fn stbiterr(&self) -> STBITERRR {
                 let bits = {
                     const MASK: bool = true;
@@ -52090,7 +52409,8 @@ pub mod sdio {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bit 23 - CE-ATA command completion signal received interrupt enable" ] # [ inline ]
+            #[doc = "Bit 23 - CE-ATA command completion signal received interrupt enable"]
+            #[inline]
             pub fn ceataendie(&self) -> CEATAENDIER {
                 let bits = {
                     const MASK: bool = true;
@@ -52342,7 +52662,8 @@ pub mod sdio {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bit 23 - CE-ATA command completion signal received interrupt enable" ] # [ inline ]
+            #[doc = "Bit 23 - CE-ATA command completion signal received interrupt enable"]
+            #[inline]
             pub fn ceataendie(&mut self) -> _CEATAENDIEW {
                 _CEATAENDIEW { w: self }
             }
@@ -52499,7 +52820,8 @@ pub mod sdio {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:23 - Remaining number of words to be written to or read from the FIFO." ] # [ inline ]
+            #[doc = "Bits 0:23 - Remaining number of words to be written to or read from the FIFO."]
+            #[inline]
             pub fn fifocount(&self) -> FIFOCOUNTR {
                 let bits = {
                     const MASK: u32 = 0x00ff_ffff;
@@ -95053,7 +95375,8 @@ pub mod dma2 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bit 27 - Stream x transfer complete interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 27 - Stream x transfer complete interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn tcif3(&self) -> TCIF3R {
                 let bits = {
                     const MASK: bool = true;
@@ -95082,7 +95405,8 @@ pub mod dma2 {
                 };
                 TEIF3R { bits }
             }
-            # [ doc = "Bit 24 - Stream x direct mode error interrupt flag (x=3..0)" ] # [ inline ]
+            #[doc = "Bit 24 - Stream x direct mode error interrupt flag (x=3..0)"]
+            #[inline]
             pub fn dmeif3(&self) -> DMEIF3R {
                 let bits = {
                     const MASK: bool = true;
@@ -95101,7 +95425,8 @@ pub mod dma2 {
                 };
                 FEIF3R { bits }
             }
-            # [ doc = "Bit 21 - Stream x transfer complete interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 21 - Stream x transfer complete interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn tcif2(&self) -> TCIF2R {
                 let bits = {
                     const MASK: bool = true;
@@ -95130,7 +95455,8 @@ pub mod dma2 {
                 };
                 TEIF2R { bits }
             }
-            # [ doc = "Bit 18 - Stream x direct mode error interrupt flag (x=3..0)" ] # [ inline ]
+            #[doc = "Bit 18 - Stream x direct mode error interrupt flag (x=3..0)"]
+            #[inline]
             pub fn dmeif2(&self) -> DMEIF2R {
                 let bits = {
                     const MASK: bool = true;
@@ -95149,7 +95475,8 @@ pub mod dma2 {
                 };
                 FEIF2R { bits }
             }
-            # [ doc = "Bit 11 - Stream x transfer complete interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 11 - Stream x transfer complete interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn tcif1(&self) -> TCIF1R {
                 let bits = {
                     const MASK: bool = true;
@@ -95198,7 +95525,8 @@ pub mod dma2 {
                 };
                 FEIF1R { bits }
             }
-            # [ doc = "Bit 5 - Stream x transfer complete interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 5 - Stream x transfer complete interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn tcif0(&self) -> TCIF0R {
                 let bits = {
                     const MASK: bool = true;
@@ -95694,7 +96022,8 @@ pub mod dma2 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bit 27 - Stream x transfer complete interrupt flag (x=7..4)" ] # [ inline ]
+            #[doc = "Bit 27 - Stream x transfer complete interrupt flag (x=7..4)"]
+            #[inline]
             pub fn tcif7(&self) -> TCIF7R {
                 let bits = {
                     const MASK: bool = true;
@@ -95723,7 +96052,8 @@ pub mod dma2 {
                 };
                 TEIF7R { bits }
             }
-            # [ doc = "Bit 24 - Stream x direct mode error interrupt flag (x=7..4)" ] # [ inline ]
+            #[doc = "Bit 24 - Stream x direct mode error interrupt flag (x=7..4)"]
+            #[inline]
             pub fn dmeif7(&self) -> DMEIF7R {
                 let bits = {
                     const MASK: bool = true;
@@ -95742,7 +96072,8 @@ pub mod dma2 {
                 };
                 FEIF7R { bits }
             }
-            # [ doc = "Bit 21 - Stream x transfer complete interrupt flag (x=7..4)" ] # [ inline ]
+            #[doc = "Bit 21 - Stream x transfer complete interrupt flag (x=7..4)"]
+            #[inline]
             pub fn tcif6(&self) -> TCIF6R {
                 let bits = {
                     const MASK: bool = true;
@@ -95771,7 +96102,8 @@ pub mod dma2 {
                 };
                 TEIF6R { bits }
             }
-            # [ doc = "Bit 18 - Stream x direct mode error interrupt flag (x=7..4)" ] # [ inline ]
+            #[doc = "Bit 18 - Stream x direct mode error interrupt flag (x=7..4)"]
+            #[inline]
             pub fn dmeif6(&self) -> DMEIF6R {
                 let bits = {
                     const MASK: bool = true;
@@ -95790,7 +96122,8 @@ pub mod dma2 {
                 };
                 FEIF6R { bits }
             }
-            # [ doc = "Bit 11 - Stream x transfer complete interrupt flag (x=7..4)" ] # [ inline ]
+            #[doc = "Bit 11 - Stream x transfer complete interrupt flag (x=7..4)"]
+            #[inline]
             pub fn tcif5(&self) -> TCIF5R {
                 let bits = {
                     const MASK: bool = true;
@@ -96385,83 +96718,103 @@ pub mod dma2 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn ctcif3(&mut self) -> _CTCIF3W {
                 _CTCIF3W { w: self }
             }
-            # [ doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn chtif3(&mut self) -> _CHTIF3W {
                 _CHTIF3W { w: self }
             }
-            # [ doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cteif3(&mut self) -> _CTEIF3W {
                 _CTEIF3W { w: self }
             }
-            # [ doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cdmeif3(&mut self) -> _CDMEIF3W {
                 _CDMEIF3W { w: self }
             }
-            # [ doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cfeif3(&mut self) -> _CFEIF3W {
                 _CFEIF3W { w: self }
             }
-            # [ doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn ctcif2(&mut self) -> _CTCIF2W {
                 _CTCIF2W { w: self }
             }
-            # [ doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn chtif2(&mut self) -> _CHTIF2W {
                 _CHTIF2W { w: self }
             }
-            # [ doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cteif2(&mut self) -> _CTEIF2W {
                 _CTEIF2W { w: self }
             }
-            # [ doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cdmeif2(&mut self) -> _CDMEIF2W {
                 _CDMEIF2W { w: self }
             }
-            # [ doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cfeif2(&mut self) -> _CFEIF2W {
                 _CFEIF2W { w: self }
             }
-            # [ doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn ctcif1(&mut self) -> _CTCIF1W {
                 _CTCIF1W { w: self }
             }
-            # [ doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn chtif1(&mut self) -> _CHTIF1W {
                 _CHTIF1W { w: self }
             }
-            # [ doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cteif1(&mut self) -> _CTEIF1W {
                 _CTEIF1W { w: self }
             }
-            # [ doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cdmeif1(&mut self) -> _CDMEIF1W {
                 _CDMEIF1W { w: self }
             }
-            # [ doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cfeif1(&mut self) -> _CFEIF1W {
                 _CFEIF1W { w: self }
             }
-            # [ doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn ctcif0(&mut self) -> _CTCIF0W {
                 _CTCIF0W { w: self }
             }
-            # [ doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn chtif0(&mut self) -> _CHTIF0W {
                 _CHTIF0W { w: self }
             }
-            # [ doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cteif0(&mut self) -> _CTEIF0W {
                 _CTEIF0W { w: self }
             }
-            # [ doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cdmeif0(&mut self) -> _CDMEIF0W {
                 _CDMEIF0W { w: self }
             }
-            # [ doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)" ] # [ inline ]
+            #[doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)"]
+            #[inline]
             pub fn cfeif0(&mut self) -> _CFEIF0W {
                 _CFEIF0W { w: self }
             }
@@ -96961,83 +97314,103 @@ pub mod dma2 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn ctcif7(&mut self) -> _CTCIF7W {
                 _CTCIF7W { w: self }
             }
-            # [ doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn chtif7(&mut self) -> _CHTIF7W {
                 _CHTIF7W { w: self }
             }
-            # [ doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cteif7(&mut self) -> _CTEIF7W {
                 _CTEIF7W { w: self }
             }
-            # [ doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cdmeif7(&mut self) -> _CDMEIF7W {
                 _CDMEIF7W { w: self }
             }
-            # [ doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cfeif7(&mut self) -> _CFEIF7W {
                 _CFEIF7W { w: self }
             }
-            # [ doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn ctcif6(&mut self) -> _CTCIF6W {
                 _CTCIF6W { w: self }
             }
-            # [ doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn chtif6(&mut self) -> _CHTIF6W {
                 _CHTIF6W { w: self }
             }
-            # [ doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cteif6(&mut self) -> _CTEIF6W {
                 _CTEIF6W { w: self }
             }
-            # [ doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cdmeif6(&mut self) -> _CDMEIF6W {
                 _CDMEIF6W { w: self }
             }
-            # [ doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cfeif6(&mut self) -> _CFEIF6W {
                 _CFEIF6W { w: self }
             }
-            # [ doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn ctcif5(&mut self) -> _CTCIF5W {
                 _CTCIF5W { w: self }
             }
-            # [ doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn chtif5(&mut self) -> _CHTIF5W {
                 _CHTIF5W { w: self }
             }
-            # [ doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cteif5(&mut self) -> _CTEIF5W {
                 _CTEIF5W { w: self }
             }
-            # [ doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cdmeif5(&mut self) -> _CDMEIF5W {
                 _CDMEIF5W { w: self }
             }
-            # [ doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cfeif5(&mut self) -> _CFEIF5W {
                 _CFEIF5W { w: self }
             }
-            # [ doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn ctcif4(&mut self) -> _CTCIF4W {
                 _CTCIF4W { w: self }
             }
-            # [ doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn chtif4(&mut self) -> _CHTIF4W {
                 _CHTIF4W { w: self }
             }
-            # [ doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cteif4(&mut self) -> _CTEIF4W {
                 _CTEIF4W { w: self }
             }
-            # [ doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cdmeif4(&mut self) -> _CDMEIF4W {
                 _CDMEIF4W { w: self }
             }
-            # [ doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)" ] # [ inline ]
+            #[doc = "Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)"]
+            #[inline]
             pub fn cfeif4(&mut self) -> _CFEIF4W {
                 _CFEIF4W { w: self }
             }
@@ -98527,7 +98900,8 @@ pub mod dma2 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&self) -> M1AR {
                 let bits = {
                     const MASK: u32 = 0xffff_ffff;
@@ -98549,7 +98923,8 @@ pub mod dma2 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&mut self) -> _M1AW {
                 _M1AW { w: self }
             }
@@ -100349,7 +100724,8 @@ pub mod dma2 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&self) -> M1AR {
                 let bits = {
                     const MASK: u32 = 0xffff_ffff;
@@ -100371,7 +100747,8 @@ pub mod dma2 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&mut self) -> _M1AW {
                 _M1AW { w: self }
             }
@@ -102171,7 +102548,8 @@ pub mod dma2 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&self) -> M1AR {
                 let bits = {
                     const MASK: u32 = 0xffff_ffff;
@@ -102193,7 +102571,8 @@ pub mod dma2 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&mut self) -> _M1AW {
                 _M1AW { w: self }
             }
@@ -103993,7 +104372,8 @@ pub mod dma2 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&self) -> M1AR {
                 let bits = {
                     const MASK: u32 = 0xffff_ffff;
@@ -104015,7 +104395,8 @@ pub mod dma2 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&mut self) -> _M1AW {
                 _M1AW { w: self }
             }
@@ -105815,7 +106196,8 @@ pub mod dma2 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&self) -> M1AR {
                 let bits = {
                     const MASK: u32 = 0xffff_ffff;
@@ -105837,7 +106219,8 @@ pub mod dma2 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&mut self) -> _M1AW {
                 _M1AW { w: self }
             }
@@ -107637,7 +108020,8 @@ pub mod dma2 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&self) -> M1AR {
                 let bits = {
                     const MASK: u32 = 0xffff_ffff;
@@ -107659,7 +108043,8 @@ pub mod dma2 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&mut self) -> _M1AW {
                 _M1AW { w: self }
             }
@@ -109459,7 +109844,8 @@ pub mod dma2 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&self) -> M1AR {
                 let bits = {
                     const MASK: u32 = 0xffff_ffff;
@@ -109481,7 +109867,8 @@ pub mod dma2 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&mut self) -> _M1AW {
                 _M1AW { w: self }
             }
@@ -111281,7 +111668,8 @@ pub mod dma2 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&self) -> M1AR {
                 let bits = {
                     const MASK: u32 = 0xffff_ffff;
@@ -111303,7 +111691,8 @@ pub mod dma2 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)" ] # [ inline ]
+            #[doc = "Bits 0:31 - Memory 1 address (used in case of Double buffer mode)"]
+            #[inline]
             pub fn m1a(&mut self) -> _M1AW {
                 _M1AW { w: self }
             }
@@ -118626,7 +119015,8 @@ pub mod gpioh {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl7(&self) -> AFRL7R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -118635,7 +119025,8 @@ pub mod gpioh {
                 };
                 AFRL7R { bits }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl6(&self) -> AFRL6R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -118644,7 +119035,8 @@ pub mod gpioh {
                 };
                 AFRL6R { bits }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl5(&self) -> AFRL5R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -118653,7 +119045,8 @@ pub mod gpioh {
                 };
                 AFRL5R { bits }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl4(&self) -> AFRL4R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -118662,7 +119055,8 @@ pub mod gpioh {
                 };
                 AFRL4R { bits }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl3(&self) -> AFRL3R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -118671,7 +119065,8 @@ pub mod gpioh {
                 };
                 AFRL3R { bits }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl2(&self) -> AFRL2R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -118680,7 +119075,8 @@ pub mod gpioh {
                 };
                 AFRL2R { bits }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl1(&self) -> AFRL1R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -118689,7 +119085,8 @@ pub mod gpioh {
                 };
                 AFRL1R { bits }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl0(&self) -> AFRL0R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -118711,35 +119108,43 @@ pub mod gpioh {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl7(&mut self) -> _AFRL7W {
                 _AFRL7W { w: self }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl6(&mut self) -> _AFRL6W {
                 _AFRL6W { w: self }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl5(&mut self) -> _AFRL5W {
                 _AFRL5W { w: self }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl4(&mut self) -> _AFRL4W {
                 _AFRL4W { w: self }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl3(&mut self) -> _AFRL3W {
                 _AFRL3W { w: self }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl2(&mut self) -> _AFRL2W {
                 _AFRL2W { w: self }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl1(&mut self) -> _AFRL1W {
                 _AFRL1W { w: self }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl0(&mut self) -> _AFRL0W {
                 _AFRL0W { w: self }
             }
@@ -119009,7 +119414,8 @@ pub mod gpioh {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh15(&self) -> AFRH15R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -119018,7 +119424,8 @@ pub mod gpioh {
                 };
                 AFRH15R { bits }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh14(&self) -> AFRH14R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -119027,7 +119434,8 @@ pub mod gpioh {
                 };
                 AFRH14R { bits }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh13(&self) -> AFRH13R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -119036,7 +119444,8 @@ pub mod gpioh {
                 };
                 AFRH13R { bits }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh12(&self) -> AFRH12R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -119045,7 +119454,8 @@ pub mod gpioh {
                 };
                 AFRH12R { bits }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh11(&self) -> AFRH11R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -119054,7 +119464,8 @@ pub mod gpioh {
                 };
                 AFRH11R { bits }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh10(&self) -> AFRH10R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -119063,7 +119474,8 @@ pub mod gpioh {
                 };
                 AFRH10R { bits }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh9(&self) -> AFRH9R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -119072,7 +119484,8 @@ pub mod gpioh {
                 };
                 AFRH9R { bits }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh8(&self) -> AFRH8R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -119094,35 +119507,43 @@ pub mod gpioh {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh15(&mut self) -> _AFRH15W {
                 _AFRH15W { w: self }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh14(&mut self) -> _AFRH14W {
                 _AFRH14W { w: self }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh13(&mut self) -> _AFRH13W {
                 _AFRH13W { w: self }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh12(&mut self) -> _AFRH12W {
                 _AFRH12W { w: self }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh11(&mut self) -> _AFRH11W {
                 _AFRH11W { w: self }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh10(&mut self) -> _AFRH10W {
                 _AFRH10W { w: self }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh9(&mut self) -> _AFRH9W {
                 _AFRH9W { w: self }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh8(&mut self) -> _AFRH8W {
                 _AFRH8W { w: self }
             }
@@ -126262,7 +126683,8 @@ pub mod gpiob {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl7(&self) -> AFRL7R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126271,7 +126693,8 @@ pub mod gpiob {
                 };
                 AFRL7R { bits }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl6(&self) -> AFRL6R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126280,7 +126703,8 @@ pub mod gpiob {
                 };
                 AFRL6R { bits }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl5(&self) -> AFRL5R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126289,7 +126713,8 @@ pub mod gpiob {
                 };
                 AFRL5R { bits }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl4(&self) -> AFRL4R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126298,7 +126723,8 @@ pub mod gpiob {
                 };
                 AFRL4R { bits }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl3(&self) -> AFRL3R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126307,7 +126733,8 @@ pub mod gpiob {
                 };
                 AFRL3R { bits }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl2(&self) -> AFRL2R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126316,7 +126743,8 @@ pub mod gpiob {
                 };
                 AFRL2R { bits }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl1(&self) -> AFRL1R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126325,7 +126753,8 @@ pub mod gpiob {
                 };
                 AFRL1R { bits }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl0(&self) -> AFRL0R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126347,35 +126776,43 @@ pub mod gpiob {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl7(&mut self) -> _AFRL7W {
                 _AFRL7W { w: self }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl6(&mut self) -> _AFRL6W {
                 _AFRL6W { w: self }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl5(&mut self) -> _AFRL5W {
                 _AFRL5W { w: self }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl4(&mut self) -> _AFRL4W {
                 _AFRL4W { w: self }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl3(&mut self) -> _AFRL3W {
                 _AFRL3W { w: self }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl2(&mut self) -> _AFRL2W {
                 _AFRL2W { w: self }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl1(&mut self) -> _AFRL1W {
                 _AFRL1W { w: self }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl0(&mut self) -> _AFRL0W {
                 _AFRL0W { w: self }
             }
@@ -126645,7 +127082,8 @@ pub mod gpiob {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh15(&self) -> AFRH15R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126654,7 +127092,8 @@ pub mod gpiob {
                 };
                 AFRH15R { bits }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh14(&self) -> AFRH14R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126663,7 +127102,8 @@ pub mod gpiob {
                 };
                 AFRH14R { bits }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh13(&self) -> AFRH13R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126672,7 +127112,8 @@ pub mod gpiob {
                 };
                 AFRH13R { bits }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh12(&self) -> AFRH12R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126681,7 +127122,8 @@ pub mod gpiob {
                 };
                 AFRH12R { bits }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh11(&self) -> AFRH11R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126690,7 +127132,8 @@ pub mod gpiob {
                 };
                 AFRH11R { bits }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh10(&self) -> AFRH10R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126699,7 +127142,8 @@ pub mod gpiob {
                 };
                 AFRH10R { bits }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh9(&self) -> AFRH9R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126708,7 +127152,8 @@ pub mod gpiob {
                 };
                 AFRH9R { bits }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh8(&self) -> AFRH8R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -126730,35 +127175,43 @@ pub mod gpiob {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh15(&mut self) -> _AFRH15W {
                 _AFRH15W { w: self }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh14(&mut self) -> _AFRH14W {
                 _AFRH14W { w: self }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh13(&mut self) -> _AFRH13W {
                 _AFRH13W { w: self }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh12(&mut self) -> _AFRH12W {
                 _AFRH12W { w: self }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh11(&mut self) -> _AFRH11W {
                 _AFRH11W { w: self }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh10(&mut self) -> _AFRH10W {
                 _AFRH10W { w: self }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh9(&mut self) -> _AFRH9W {
                 _AFRH9W { w: self }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh8(&mut self) -> _AFRH8W {
                 _AFRH8W { w: self }
             }
@@ -133813,7 +134266,8 @@ pub mod gpioa {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl7(&self) -> AFRL7R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -133822,7 +134276,8 @@ pub mod gpioa {
                 };
                 AFRL7R { bits }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl6(&self) -> AFRL6R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -133831,7 +134286,8 @@ pub mod gpioa {
                 };
                 AFRL6R { bits }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl5(&self) -> AFRL5R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -133840,7 +134296,8 @@ pub mod gpioa {
                 };
                 AFRL5R { bits }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl4(&self) -> AFRL4R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -133849,7 +134306,8 @@ pub mod gpioa {
                 };
                 AFRL4R { bits }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl3(&self) -> AFRL3R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -133858,7 +134316,8 @@ pub mod gpioa {
                 };
                 AFRL3R { bits }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl2(&self) -> AFRL2R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -133867,7 +134326,8 @@ pub mod gpioa {
                 };
                 AFRL2R { bits }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl1(&self) -> AFRL1R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -133876,7 +134336,8 @@ pub mod gpioa {
                 };
                 AFRL1R { bits }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl0(&self) -> AFRL0R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -133898,35 +134359,43 @@ pub mod gpioa {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl7(&mut self) -> _AFRL7W {
                 _AFRL7W { w: self }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl6(&mut self) -> _AFRL6W {
                 _AFRL6W { w: self }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl5(&mut self) -> _AFRL5W {
                 _AFRL5W { w: self }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl4(&mut self) -> _AFRL4W {
                 _AFRL4W { w: self }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl3(&mut self) -> _AFRL3W {
                 _AFRL3W { w: self }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl2(&mut self) -> _AFRL2W {
                 _AFRL2W { w: self }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl1(&mut self) -> _AFRL1W {
                 _AFRL1W { w: self }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)"]
+            #[inline]
             pub fn afrl0(&mut self) -> _AFRL0W {
                 _AFRL0W { w: self }
             }
@@ -134196,7 +134665,8 @@ pub mod gpioa {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh15(&self) -> AFRH15R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -134205,7 +134675,8 @@ pub mod gpioa {
                 };
                 AFRH15R { bits }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh14(&self) -> AFRH14R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -134214,7 +134685,8 @@ pub mod gpioa {
                 };
                 AFRH14R { bits }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh13(&self) -> AFRH13R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -134223,7 +134695,8 @@ pub mod gpioa {
                 };
                 AFRH13R { bits }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh12(&self) -> AFRH12R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -134232,7 +134705,8 @@ pub mod gpioa {
                 };
                 AFRH12R { bits }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh11(&self) -> AFRH11R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -134241,7 +134715,8 @@ pub mod gpioa {
                 };
                 AFRH11R { bits }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh10(&self) -> AFRH10R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -134250,7 +134725,8 @@ pub mod gpioa {
                 };
                 AFRH10R { bits }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh9(&self) -> AFRH9R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -134259,7 +134735,8 @@ pub mod gpioa {
                 };
                 AFRH9R { bits }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh8(&self) -> AFRH8R {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -134281,35 +134758,43 @@ pub mod gpioa {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh15(&mut self) -> _AFRH15W {
                 _AFRH15W { w: self }
             }
-            # [ doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh14(&mut self) -> _AFRH14W {
                 _AFRH14W { w: self }
             }
-            # [ doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh13(&mut self) -> _AFRH13W {
                 _AFRH13W { w: self }
             }
-            # [ doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh12(&mut self) -> _AFRH12W {
                 _AFRH12W { w: self }
             }
-            # [ doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh11(&mut self) -> _AFRH11W {
                 _AFRH11W { w: self }
             }
-            # [ doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh10(&mut self) -> _AFRH10W {
                 _AFRH10W { w: self }
             }
-            # [ doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh9(&mut self) -> _AFRH9W {
                 _AFRH9W { w: self }
             }
-            # [ doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)" ] # [ inline ]
+            #[doc = "Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)"]
+            #[inline]
             pub fn afrh8(&mut self) -> _AFRH8W {
                 _AFRH8W { w: self }
             }
@@ -137372,7 +137857,8 @@ pub mod i2c3 {
                 };
                 DUTYR { bits }
             }
-            # [ doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)" ] # [ inline ]
+            #[doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)"]
+            #[inline]
             pub fn ccr(&self) -> CCRR {
                 let bits = {
                     const MASK: u16 = 0x0fff;
@@ -137404,7 +137890,8 @@ pub mod i2c3 {
             pub fn duty(&mut self) -> _DUTYW {
                 _DUTYW { w: self }
             }
-            # [ doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)" ] # [ inline ]
+            #[doc = "Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)"]
+            #[inline]
             pub fn ccr(&mut self) -> _CCRW {
                 _CCRW { w: self }
             }
@@ -137492,7 +137979,8 @@ pub mod i2c3 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)" ] # [ inline ]
+            #[doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)"]
+            #[inline]
             pub fn trise(&self) -> TRISER {
                 let bits = {
                     const MASK: u8 = 0x3f;
@@ -137514,7 +138002,8 @@ pub mod i2c3 {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)" ] # [ inline ]
+            #[doc = "Bits 0:5 - Maximum rise time in Fast/Standard mode (Master mode)"]
+            #[inline]
             pub fn trise(&mut self) -> _TRISEW {
                 _TRISEW { w: self }
             }
@@ -150511,7 +151000,8 @@ pub mod dfsdm1 {
                 };
                 AWFSELR { bits }
             }
-            # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ]
+            #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
+            #[inline]
             pub fn fast(&self) -> FASTR {
                 let bits = {
                     const MASK: bool = true;
@@ -150530,7 +151020,8 @@ pub mod dfsdm1 {
                 };
                 RCHR { bits }
             }
-            # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ]
+            #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
+            #[inline]
             pub fn rdmaen(&self) -> RDMAENR {
                 let bits = {
                     const MASK: bool = true;
@@ -150539,7 +151030,8 @@ pub mod dfsdm1 {
                 };
                 RDMAENR { bits }
             }
-            # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ]
+            #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
+            #[inline]
             pub fn rsync(&self) -> RSYNCR {
                 let bits = {
                     const MASK: bool = true;
@@ -150558,7 +151050,8 @@ pub mod dfsdm1 {
                 };
                 RCONTR { bits }
             }
-            # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ]
+            #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
+            #[inline]
             pub fn rswstart(&self) -> RSWSTARTR {
                 let bits = {
                     const MASK: bool = true;
@@ -150567,7 +151060,8 @@ pub mod dfsdm1 {
                 };
                 RSWSTARTR { bits }
             }
-            # [ doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions" ] # [ inline ]
+            #[doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions"]
+            #[inline]
             pub fn jexten(&self) -> JEXTENR {
                 let bits = {
                     const MASK: u8 = 0x03;
@@ -150576,7 +151070,8 @@ pub mod dfsdm1 {
                 };
                 JEXTENR { bits }
             }
-            # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ]
+            #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
+            #[inline]
             pub fn jextsel(&self) -> JEXTSELR {
                 let bits = {
                     const MASK: u8 = 0x07;
@@ -150585,7 +151080,8 @@ pub mod dfsdm1 {
                 };
                 JEXTSELR { bits }
             }
-            # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ]
+            #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
+            #[inline]
             pub fn jdmaen(&self) -> JDMAENR {
                 let bits = {
                     const MASK: bool = true;
@@ -150604,7 +151100,8 @@ pub mod dfsdm1 {
                 };
                 JSCANR { bits }
             }
-            # [ doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" ] # [ inline ]
+            #[doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
+            #[inline]
             pub fn jsync(&self) -> JSYNCR {
                 let bits = {
                     const MASK: bool = true;
@@ -150613,7 +151110,8 @@ pub mod dfsdm1 {
                 };
                 JSYNCR { bits }
             }
-            # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ]
+            #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
+            #[inline]
             pub fn jswstart(&self) -> JSWSTARTR {
                 let bits = {
                     const MASK: bool = true;
@@ -150650,7 +151148,8 @@ pub mod dfsdm1 {
             pub fn awfsel(&mut self) -> _AWFSELW {
                 _AWFSELW { w: self }
             }
-            # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ]
+            #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
+            #[inline]
             pub fn fast(&mut self) -> _FASTW {
                 _FASTW { w: self }
             }
@@ -150659,11 +151158,13 @@ pub mod dfsdm1 {
             pub fn rch(&mut self) -> _RCHW {
                 _RCHW { w: self }
             }
-            # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ]
+            #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
+            #[inline]
             pub fn rdmaen(&mut self) -> _RDMAENW {
                 _RDMAENW { w: self }
             }
-            # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ]
+            #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
+            #[inline]
             pub fn rsync(&mut self) -> _RSYNCW {
                 _RSYNCW { w: self }
             }
@@ -150672,19 +151173,23 @@ pub mod dfsdm1 {
             pub fn rcont(&mut self) -> _RCONTW {
                 _RCONTW { w: self }
             }
-            # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ]
+            #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
+            #[inline]
             pub fn rswstart(&mut self) -> _RSWSTARTW {
                 _RSWSTARTW { w: self }
             }
-            # [ doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions" ] # [ inline ]
+            #[doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions"]
+            #[inline]
             pub fn jexten(&mut self) -> _JEXTENW {
                 _JEXTENW { w: self }
             }
-            # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ]
+            #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
+            #[inline]
             pub fn jextsel(&mut self) -> _JEXTSELW {
                 _JEXTSELW { w: self }
             }
-            # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ]
+            #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
+            #[inline]
             pub fn jdmaen(&mut self) -> _JDMAENW {
                 _JDMAENW { w: self }
             }
@@ -150693,11 +151198,13 @@ pub mod dfsdm1 {
             pub fn jscan(&mut self) -> _JSCANW {
                 _JSCANW { w: self }
             }
-            # [ doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" ] # [ inline ]
+            #[doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
+            #[inline]
             pub fn jsync(&mut self) -> _JSYNCW {
                 _JSYNCW { w: self }
             }
-            # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ]
+            #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
+            #[inline]
             pub fn jswstart(&mut self) -> _JSWSTARTW {
                 _JSWSTARTW { w: self }
             }
@@ -152087,7 +152594,8 @@ pub mod dfsdm1 {
                 };
                 FORDR { bits }
             }
-            # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ]
+            #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
+            #[inline]
             pub fn fosr(&self) -> FOSRR {
                 let bits = {
                     const MASK: u16 = 0x03ff;
@@ -152096,7 +152604,8 @@ pub mod dfsdm1 {
                 };
                 FOSRR { bits }
             }
-            # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ]
+            #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
+            #[inline]
             pub fn iosr(&self) -> IOSRR {
                 let bits = {
                     const MASK: u8 = 0xff;
@@ -152123,11 +152632,13 @@ pub mod dfsdm1 {
             pub fn ford(&mut self) -> _FORDW {
                 _FORDW { w: self }
             }
-            # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ]
+            #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
+            #[inline]
             pub fn fosr(&mut self) -> _FOSRW {
                 _FOSRW { w: self }
             }
-            # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ]
+            #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
+            #[inline]
             pub fn iosr(&mut self) -> _IOSRW {
                 _IOSRW { w: self }
             }
@@ -152420,7 +152931,8 @@ pub mod dfsdm1 {
                 };
                 AWHTR { bits }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
+            #[inline]
             pub fn bkawh(&self) -> BKAWHR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -152447,7 +152959,8 @@ pub mod dfsdm1 {
             pub fn awht(&mut self) -> _AWHTW {
                 _AWHTW { w: self }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
+            #[inline]
             pub fn bkawh(&mut self) -> _BKAWHW {
                 _BKAWHW { w: self }
             }
@@ -152571,7 +153084,8 @@ pub mod dfsdm1 {
                 };
                 AWLTR { bits }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
+            #[inline]
             pub fn bkawl(&self) -> BKAWLR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -152598,7 +153112,8 @@ pub mod dfsdm1 {
             pub fn awlt(&mut self) -> _AWLTW {
                 _AWLTW { w: self }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
+            #[inline]
             pub fn bkawl(&mut self) -> _BKAWLW {
                 _BKAWLW { w: self }
             }
@@ -153000,7 +153515,8 @@ pub mod dfsdm1 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 4:31 - 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN" ] # [ inline ]
+            #[doc = "Bits 4:31 - 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"]
+            #[inline]
             pub fn cnvcnt(&self) -> CNVCNTR {
                 let bits = {
                     const MASK: u32 = 0x0fff_ffff;
@@ -153639,7 +154155,8 @@ pub mod dfsdm1 {
                 };
                 AWFSELR { bits }
             }
-            # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ]
+            #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
+            #[inline]
             pub fn fast(&self) -> FASTR {
                 let bits = {
                     const MASK: bool = true;
@@ -153658,7 +154175,8 @@ pub mod dfsdm1 {
                 };
                 RCHR { bits }
             }
-            # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ]
+            #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
+            #[inline]
             pub fn rdmaen(&self) -> RDMAENR {
                 let bits = {
                     const MASK: bool = true;
@@ -153667,7 +154185,8 @@ pub mod dfsdm1 {
                 };
                 RDMAENR { bits }
             }
-            # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ]
+            #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
+            #[inline]
             pub fn rsync(&self) -> RSYNCR {
                 let bits = {
                     const MASK: bool = true;
@@ -153686,7 +154205,8 @@ pub mod dfsdm1 {
                 };
                 RCONTR { bits }
             }
-            # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ]
+            #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
+            #[inline]
             pub fn rswstart(&self) -> RSWSTARTR {
                 let bits = {
                     const MASK: bool = true;
@@ -153695,7 +154215,8 @@ pub mod dfsdm1 {
                 };
                 RSWSTARTR { bits }
             }
-            # [ doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions" ] # [ inline ]
+            #[doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions"]
+            #[inline]
             pub fn jexten(&self) -> JEXTENR {
                 let bits = {
                     const MASK: u8 = 0x03;
@@ -153704,7 +154225,8 @@ pub mod dfsdm1 {
                 };
                 JEXTENR { bits }
             }
-            # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ]
+            #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
+            #[inline]
             pub fn jextsel(&self) -> JEXTSELR {
                 let bits = {
                     const MASK: u8 = 0x07;
@@ -153713,7 +154235,8 @@ pub mod dfsdm1 {
                 };
                 JEXTSELR { bits }
             }
-            # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ]
+            #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
+            #[inline]
             pub fn jdmaen(&self) -> JDMAENR {
                 let bits = {
                     const MASK: bool = true;
@@ -153732,7 +154255,8 @@ pub mod dfsdm1 {
                 };
                 JSCANR { bits }
             }
-            # [ doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" ] # [ inline ]
+            #[doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
+            #[inline]
             pub fn jsync(&self) -> JSYNCR {
                 let bits = {
                     const MASK: bool = true;
@@ -153741,7 +154265,8 @@ pub mod dfsdm1 {
                 };
                 JSYNCR { bits }
             }
-            # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ]
+            #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
+            #[inline]
             pub fn jswstart(&self) -> JSWSTARTR {
                 let bits = {
                     const MASK: bool = true;
@@ -153778,7 +154303,8 @@ pub mod dfsdm1 {
             pub fn awfsel(&mut self) -> _AWFSELW {
                 _AWFSELW { w: self }
             }
-            # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ]
+            #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
+            #[inline]
             pub fn fast(&mut self) -> _FASTW {
                 _FASTW { w: self }
             }
@@ -153787,11 +154313,13 @@ pub mod dfsdm1 {
             pub fn rch(&mut self) -> _RCHW {
                 _RCHW { w: self }
             }
-            # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ]
+            #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
+            #[inline]
             pub fn rdmaen(&mut self) -> _RDMAENW {
                 _RDMAENW { w: self }
             }
-            # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ]
+            #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
+            #[inline]
             pub fn rsync(&mut self) -> _RSYNCW {
                 _RSYNCW { w: self }
             }
@@ -153800,19 +154328,23 @@ pub mod dfsdm1 {
             pub fn rcont(&mut self) -> _RCONTW {
                 _RCONTW { w: self }
             }
-            # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ]
+            #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
+            #[inline]
             pub fn rswstart(&mut self) -> _RSWSTARTW {
                 _RSWSTARTW { w: self }
             }
-            # [ doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions" ] # [ inline ]
+            #[doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions"]
+            #[inline]
             pub fn jexten(&mut self) -> _JEXTENW {
                 _JEXTENW { w: self }
             }
-            # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ]
+            #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
+            #[inline]
             pub fn jextsel(&mut self) -> _JEXTSELW {
                 _JEXTSELW { w: self }
             }
-            # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ]
+            #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
+            #[inline]
             pub fn jdmaen(&mut self) -> _JDMAENW {
                 _JDMAENW { w: self }
             }
@@ -153821,11 +154353,13 @@ pub mod dfsdm1 {
             pub fn jscan(&mut self) -> _JSCANW {
                 _JSCANW { w: self }
             }
-            # [ doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" ] # [ inline ]
+            #[doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
+            #[inline]
             pub fn jsync(&mut self) -> _JSYNCW {
                 _JSYNCW { w: self }
             }
-            # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ]
+            #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
+            #[inline]
             pub fn jswstart(&mut self) -> _JSWSTARTW {
                 _JSWSTARTW { w: self }
             }
@@ -155215,7 +155749,8 @@ pub mod dfsdm1 {
                 };
                 FORDR { bits }
             }
-            # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ]
+            #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
+            #[inline]
             pub fn fosr(&self) -> FOSRR {
                 let bits = {
                     const MASK: u16 = 0x03ff;
@@ -155224,7 +155759,8 @@ pub mod dfsdm1 {
                 };
                 FOSRR { bits }
             }
-            # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ]
+            #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
+            #[inline]
             pub fn iosr(&self) -> IOSRR {
                 let bits = {
                     const MASK: u8 = 0xff;
@@ -155251,11 +155787,13 @@ pub mod dfsdm1 {
             pub fn ford(&mut self) -> _FORDW {
                 _FORDW { w: self }
             }
-            # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ]
+            #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
+            #[inline]
             pub fn fosr(&mut self) -> _FOSRW {
                 _FOSRW { w: self }
             }
-            # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ]
+            #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
+            #[inline]
             pub fn iosr(&mut self) -> _IOSRW {
                 _IOSRW { w: self }
             }
@@ -155548,7 +156086,8 @@ pub mod dfsdm1 {
                 };
                 AWHTR { bits }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
+            #[inline]
             pub fn bkawh(&self) -> BKAWHR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -155575,7 +156114,8 @@ pub mod dfsdm1 {
             pub fn awht(&mut self) -> _AWHTW {
                 _AWHTW { w: self }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
+            #[inline]
             pub fn bkawh(&mut self) -> _BKAWHW {
                 _BKAWHW { w: self }
             }
@@ -155699,7 +156239,8 @@ pub mod dfsdm1 {
                 };
                 AWLTR { bits }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
+            #[inline]
             pub fn bkawl(&self) -> BKAWLR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -155726,7 +156267,8 @@ pub mod dfsdm1 {
             pub fn awlt(&mut self) -> _AWLTW {
                 _AWLTW { w: self }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
+            #[inline]
             pub fn bkawl(&mut self) -> _BKAWLW {
                 _BKAWLW { w: self }
             }
@@ -156128,7 +156670,8 @@ pub mod dfsdm1 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 4:31 - 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN" ] # [ inline ]
+            #[doc = "Bits 4:31 - 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"]
+            #[inline]
             pub fn cnvcnt(&self) -> CNVCNTR {
                 let bits = {
                     const MASK: u32 = 0x0fff_ffff;
@@ -156767,7 +157310,8 @@ pub mod dfsdm1 {
                 };
                 AWFSELR { bits }
             }
-            # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ]
+            #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
+            #[inline]
             pub fn fast(&self) -> FASTR {
                 let bits = {
                     const MASK: bool = true;
@@ -156786,7 +157330,8 @@ pub mod dfsdm1 {
                 };
                 RCHR { bits }
             }
-            # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ]
+            #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
+            #[inline]
             pub fn rdmaen(&self) -> RDMAENR {
                 let bits = {
                     const MASK: bool = true;
@@ -156795,7 +157340,8 @@ pub mod dfsdm1 {
                 };
                 RDMAENR { bits }
             }
-            # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ]
+            #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
+            #[inline]
             pub fn rsync(&self) -> RSYNCR {
                 let bits = {
                     const MASK: bool = true;
@@ -156814,7 +157360,8 @@ pub mod dfsdm1 {
                 };
                 RCONTR { bits }
             }
-            # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ]
+            #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
+            #[inline]
             pub fn rswstart(&self) -> RSWSTARTR {
                 let bits = {
                     const MASK: bool = true;
@@ -156823,7 +157370,8 @@ pub mod dfsdm1 {
                 };
                 RSWSTARTR { bits }
             }
-            # [ doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions" ] # [ inline ]
+            #[doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions"]
+            #[inline]
             pub fn jexten(&self) -> JEXTENR {
                 let bits = {
                     const MASK: u8 = 0x03;
@@ -156832,7 +157380,8 @@ pub mod dfsdm1 {
                 };
                 JEXTENR { bits }
             }
-            # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ]
+            #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
+            #[inline]
             pub fn jextsel(&self) -> JEXTSELR {
                 let bits = {
                     const MASK: u8 = 0x07;
@@ -156841,7 +157390,8 @@ pub mod dfsdm1 {
                 };
                 JEXTSELR { bits }
             }
-            # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ]
+            #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
+            #[inline]
             pub fn jdmaen(&self) -> JDMAENR {
                 let bits = {
                     const MASK: bool = true;
@@ -156860,7 +157410,8 @@ pub mod dfsdm1 {
                 };
                 JSCANR { bits }
             }
-            # [ doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" ] # [ inline ]
+            #[doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
+            #[inline]
             pub fn jsync(&self) -> JSYNCR {
                 let bits = {
                     const MASK: bool = true;
@@ -156869,7 +157420,8 @@ pub mod dfsdm1 {
                 };
                 JSYNCR { bits }
             }
-            # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ]
+            #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
+            #[inline]
             pub fn jswstart(&self) -> JSWSTARTR {
                 let bits = {
                     const MASK: bool = true;
@@ -156906,7 +157458,8 @@ pub mod dfsdm1 {
             pub fn awfsel(&mut self) -> _AWFSELW {
                 _AWFSELW { w: self }
             }
-            # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ]
+            #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
+            #[inline]
             pub fn fast(&mut self) -> _FASTW {
                 _FASTW { w: self }
             }
@@ -156915,11 +157468,13 @@ pub mod dfsdm1 {
             pub fn rch(&mut self) -> _RCHW {
                 _RCHW { w: self }
             }
-            # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ]
+            #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
+            #[inline]
             pub fn rdmaen(&mut self) -> _RDMAENW {
                 _RDMAENW { w: self }
             }
-            # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ]
+            #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
+            #[inline]
             pub fn rsync(&mut self) -> _RSYNCW {
                 _RSYNCW { w: self }
             }
@@ -156928,19 +157483,23 @@ pub mod dfsdm1 {
             pub fn rcont(&mut self) -> _RCONTW {
                 _RCONTW { w: self }
             }
-            # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ]
+            #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
+            #[inline]
             pub fn rswstart(&mut self) -> _RSWSTARTW {
                 _RSWSTARTW { w: self }
             }
-            # [ doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions" ] # [ inline ]
+            #[doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions"]
+            #[inline]
             pub fn jexten(&mut self) -> _JEXTENW {
                 _JEXTENW { w: self }
             }
-            # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ]
+            #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
+            #[inline]
             pub fn jextsel(&mut self) -> _JEXTSELW {
                 _JEXTSELW { w: self }
             }
-            # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ]
+            #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
+            #[inline]
             pub fn jdmaen(&mut self) -> _JDMAENW {
                 _JDMAENW { w: self }
             }
@@ -156949,11 +157508,13 @@ pub mod dfsdm1 {
             pub fn jscan(&mut self) -> _JSCANW {
                 _JSCANW { w: self }
             }
-            # [ doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" ] # [ inline ]
+            #[doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
+            #[inline]
             pub fn jsync(&mut self) -> _JSYNCW {
                 _JSYNCW { w: self }
             }
-            # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ]
+            #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
+            #[inline]
             pub fn jswstart(&mut self) -> _JSWSTARTW {
                 _JSWSTARTW { w: self }
             }
@@ -158343,7 +158904,8 @@ pub mod dfsdm1 {
                 };
                 FORDR { bits }
             }
-            # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ]
+            #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
+            #[inline]
             pub fn fosr(&self) -> FOSRR {
                 let bits = {
                     const MASK: u16 = 0x03ff;
@@ -158352,7 +158914,8 @@ pub mod dfsdm1 {
                 };
                 FOSRR { bits }
             }
-            # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ]
+            #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
+            #[inline]
             pub fn iosr(&self) -> IOSRR {
                 let bits = {
                     const MASK: u8 = 0xff;
@@ -158379,11 +158942,13 @@ pub mod dfsdm1 {
             pub fn ford(&mut self) -> _FORDW {
                 _FORDW { w: self }
             }
-            # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ]
+            #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
+            #[inline]
             pub fn fosr(&mut self) -> _FOSRW {
                 _FOSRW { w: self }
             }
-            # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ]
+            #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
+            #[inline]
             pub fn iosr(&mut self) -> _IOSRW {
                 _IOSRW { w: self }
             }
@@ -158676,7 +159241,8 @@ pub mod dfsdm1 {
                 };
                 AWHTR { bits }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
+            #[inline]
             pub fn bkawh(&self) -> BKAWHR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -158703,7 +159269,8 @@ pub mod dfsdm1 {
             pub fn awht(&mut self) -> _AWHTW {
                 _AWHTW { w: self }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
+            #[inline]
             pub fn bkawh(&mut self) -> _BKAWHW {
                 _BKAWHW { w: self }
             }
@@ -158827,7 +159394,8 @@ pub mod dfsdm1 {
                 };
                 AWLTR { bits }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
+            #[inline]
             pub fn bkawl(&self) -> BKAWLR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -158854,7 +159422,8 @@ pub mod dfsdm1 {
             pub fn awlt(&mut self) -> _AWLTW {
                 _AWLTW { w: self }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
+            #[inline]
             pub fn bkawl(&mut self) -> _BKAWLW {
                 _BKAWLW { w: self }
             }
@@ -159256,7 +159825,8 @@ pub mod dfsdm1 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 4:31 - 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN" ] # [ inline ]
+            #[doc = "Bits 4:31 - 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"]
+            #[inline]
             pub fn cnvcnt(&self) -> CNVCNTR {
                 let bits = {
                     const MASK: u32 = 0x0fff_ffff;
@@ -159895,7 +160465,8 @@ pub mod dfsdm1 {
                 };
                 AWFSELR { bits }
             }
-            # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ]
+            #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
+            #[inline]
             pub fn fast(&self) -> FASTR {
                 let bits = {
                     const MASK: bool = true;
@@ -159914,7 +160485,8 @@ pub mod dfsdm1 {
                 };
                 RCHR { bits }
             }
-            # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ]
+            #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
+            #[inline]
             pub fn rdmaen(&self) -> RDMAENR {
                 let bits = {
                     const MASK: bool = true;
@@ -159923,7 +160495,8 @@ pub mod dfsdm1 {
                 };
                 RDMAENR { bits }
             }
-            # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ]
+            #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
+            #[inline]
             pub fn rsync(&self) -> RSYNCR {
                 let bits = {
                     const MASK: bool = true;
@@ -159942,7 +160515,8 @@ pub mod dfsdm1 {
                 };
                 RCONTR { bits }
             }
-            # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ]
+            #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
+            #[inline]
             pub fn rswstart(&self) -> RSWSTARTR {
                 let bits = {
                     const MASK: bool = true;
@@ -159951,7 +160525,8 @@ pub mod dfsdm1 {
                 };
                 RSWSTARTR { bits }
             }
-            # [ doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions" ] # [ inline ]
+            #[doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions"]
+            #[inline]
             pub fn jexten(&self) -> JEXTENR {
                 let bits = {
                     const MASK: u8 = 0x03;
@@ -159960,7 +160535,8 @@ pub mod dfsdm1 {
                 };
                 JEXTENR { bits }
             }
-            # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ]
+            #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
+            #[inline]
             pub fn jextsel(&self) -> JEXTSELR {
                 let bits = {
                     const MASK: u8 = 0x07;
@@ -159969,7 +160545,8 @@ pub mod dfsdm1 {
                 };
                 JEXTSELR { bits }
             }
-            # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ]
+            #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
+            #[inline]
             pub fn jdmaen(&self) -> JDMAENR {
                 let bits = {
                     const MASK: bool = true;
@@ -159988,7 +160565,8 @@ pub mod dfsdm1 {
                 };
                 JSCANR { bits }
             }
-            # [ doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" ] # [ inline ]
+            #[doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
+            #[inline]
             pub fn jsync(&self) -> JSYNCR {
                 let bits = {
                     const MASK: bool = true;
@@ -159997,7 +160575,8 @@ pub mod dfsdm1 {
                 };
                 JSYNCR { bits }
             }
-            # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ]
+            #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
+            #[inline]
             pub fn jswstart(&self) -> JSWSTARTR {
                 let bits = {
                     const MASK: bool = true;
@@ -160034,7 +160613,8 @@ pub mod dfsdm1 {
             pub fn awfsel(&mut self) -> _AWFSELW {
                 _AWFSELW { w: self }
             }
-            # [ doc = "Bit 29 - Fast conversion mode selection for regular conversions" ] # [ inline ]
+            #[doc = "Bit 29 - Fast conversion mode selection for regular conversions"]
+            #[inline]
             pub fn fast(&mut self) -> _FASTW {
                 _FASTW { w: self }
             }
@@ -160043,11 +160623,13 @@ pub mod dfsdm1 {
             pub fn rch(&mut self) -> _RCHW {
                 _RCHW { w: self }
             }
-            # [ doc = "Bit 21 - DMA channel enabled to read data for the regular conversion" ] # [ inline ]
+            #[doc = "Bit 21 - DMA channel enabled to read data for the regular conversion"]
+            #[inline]
             pub fn rdmaen(&mut self) -> _RDMAENW {
                 _RDMAENW { w: self }
             }
-            # [ doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0" ] # [ inline ]
+            #[doc = "Bit 19 - Launch regular conversion synchronously with DFSDM0"]
+            #[inline]
             pub fn rsync(&mut self) -> _RSYNCW {
                 _RSYNCW { w: self }
             }
@@ -160056,19 +160638,23 @@ pub mod dfsdm1 {
             pub fn rcont(&mut self) -> _RCONTW {
                 _RCONTW { w: self }
             }
-            # [ doc = "Bit 17 - Software start of a conversion on the regular channel" ] # [ inline ]
+            #[doc = "Bit 17 - Software start of a conversion on the regular channel"]
+            #[inline]
             pub fn rswstart(&mut self) -> _RSWSTARTW {
                 _RSWSTARTW { w: self }
             }
-            # [ doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions" ] # [ inline ]
+            #[doc = "Bits 13:14 - Trigger enable and trigger edge selection for injected conversions"]
+            #[inline]
             pub fn jexten(&mut self) -> _JEXTENW {
                 _JEXTENW { w: self }
             }
-            # [ doc = "Bits 8:10 - Trigger signal selection for launching injected conversions" ] # [ inline ]
+            #[doc = "Bits 8:10 - Trigger signal selection for launching injected conversions"]
+            #[inline]
             pub fn jextsel(&mut self) -> _JEXTSELW {
                 _JEXTSELW { w: self }
             }
-            # [ doc = "Bit 5 - DMA channel enabled to read data for the injected channel group" ] # [ inline ]
+            #[doc = "Bit 5 - DMA channel enabled to read data for the injected channel group"]
+            #[inline]
             pub fn jdmaen(&mut self) -> _JDMAENW {
                 _JDMAENW { w: self }
             }
@@ -160077,11 +160663,13 @@ pub mod dfsdm1 {
             pub fn jscan(&mut self) -> _JSCANW {
                 _JSCANW { w: self }
             }
-            # [ doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" ] # [ inline ]
+            #[doc = "Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger"]
+            #[inline]
             pub fn jsync(&mut self) -> _JSYNCW {
                 _JSYNCW { w: self }
             }
-            # [ doc = "Bit 1 - Start a conversion of the injected group of channels" ] # [ inline ]
+            #[doc = "Bit 1 - Start a conversion of the injected group of channels"]
+            #[inline]
             pub fn jswstart(&mut self) -> _JSWSTARTW {
                 _JSWSTARTW { w: self }
             }
@@ -161471,7 +162059,8 @@ pub mod dfsdm1 {
                 };
                 FORDR { bits }
             }
-            # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ]
+            #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
+            #[inline]
             pub fn fosr(&self) -> FOSRR {
                 let bits = {
                     const MASK: u16 = 0x03ff;
@@ -161480,7 +162069,8 @@ pub mod dfsdm1 {
                 };
                 FOSRR { bits }
             }
-            # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ]
+            #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
+            #[inline]
             pub fn iosr(&self) -> IOSRR {
                 let bits = {
                     const MASK: u8 = 0xff;
@@ -161507,11 +162097,13 @@ pub mod dfsdm1 {
             pub fn ford(&mut self) -> _FORDW {
                 _FORDW { w: self }
             }
-            # [ doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)" ] # [ inline ]
+            #[doc = "Bits 16:25 - Sinc filter oversampling ratio (decimation rate)"]
+            #[inline]
             pub fn fosr(&mut self) -> _FOSRW {
                 _FOSRW { w: self }
             }
-            # [ doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)" ] # [ inline ]
+            #[doc = "Bits 0:7 - Integrator oversampling ratio (averaging length)"]
+            #[inline]
             pub fn iosr(&mut self) -> _IOSRW {
                 _IOSRW { w: self }
             }
@@ -161804,7 +162396,8 @@ pub mod dfsdm1 {
                 };
                 AWHTR { bits }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
+            #[inline]
             pub fn bkawh(&self) -> BKAWHR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -161831,7 +162424,8 @@ pub mod dfsdm1 {
             pub fn awht(&mut self) -> _AWHTW {
                 _AWHTW { w: self }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog high threshold event"]
+            #[inline]
             pub fn bkawh(&mut self) -> _BKAWHW {
                 _BKAWHW { w: self }
             }
@@ -161955,7 +162549,8 @@ pub mod dfsdm1 {
                 };
                 AWLTR { bits }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
+            #[inline]
             pub fn bkawl(&self) -> BKAWLR {
                 let bits = {
                     const MASK: u8 = 0x0f;
@@ -161982,7 +162577,8 @@ pub mod dfsdm1 {
             pub fn awlt(&mut self) -> _AWLTW {
                 _AWLTW { w: self }
             }
-            # [ doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event" ] # [ inline ]
+            #[doc = "Bits 0:3 - Break signal assignment to analog watchdog low threshold event"]
+            #[inline]
             pub fn bkawl(&mut self) -> _BKAWLW {
                 _BKAWLW { w: self }
             }
@@ -162384,7 +162980,8 @@ pub mod dfsdm1 {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 4:31 - 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN" ] # [ inline ]
+            #[doc = "Bits 4:31 - 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN"]
+            #[inline]
             pub fn cnvcnt(&self) -> CNVCNTR {
                 let bits = {
                     const MASK: u32 = 0x0fff_ffff;
@@ -309972,7 +310569,45 @@ pub mod otg_fs_global {
     use vcell::VolatileCell;
     #[doc = r" Register block"]
     #[repr(C)]
-    pub struct RegisterBlock { # [ doc = "0x00 - OTG_FS control and status register (OTG_FS_GOTGCTL)" ] pub fs_gotgctl : FS_GOTGCTL , # [ doc = "0x04 - OTG_FS interrupt register (OTG_FS_GOTGINT)" ] pub fs_gotgint : FS_GOTGINT , # [ doc = "0x08 - OTG_FS AHB configuration register (OTG_FS_GAHBCFG)" ] pub fs_gahbcfg : FS_GAHBCFG , # [ doc = "0x0c - OTG_FS USB configuration register (OTG_FS_GUSBCFG)" ] pub fs_gusbcfg : FS_GUSBCFG , # [ doc = "0x10 - OTG_FS reset register (OTG_FS_GRSTCTL)" ] pub fs_grstctl : FS_GRSTCTL , # [ doc = "0x14 - OTG_FS core interrupt register (OTG_FS_GINTSTS)" ] pub fs_gintsts : FS_GINTSTS , # [ doc = "0x18 - OTG_FS interrupt mask register (OTG_FS_GINTMSK)" ] pub fs_gintmsk : FS_GINTMSK , # [ doc = "0x1c - OTG_FS Receive status debug read(Device mode)" ] pub fs_grxstsr_device : FS_GRXSTSR_DEVICE , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x24 - OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)" ] pub fs_grxfsiz : FS_GRXFSIZ , # [ doc = "0x28 - OTG_FS non-periodic transmit FIFO size register (Device mode)" ] pub fs_gnptxfsiz_device : FS_GNPTXFSIZ_DEVICE , # [ doc = "0x2c - OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)" ] pub fs_gnptxsts : FS_GNPTXSTS , _reserved1 : [ u8 ; 8usize ] , # [ doc = "0x38 - OTG_FS general core configuration register (OTG_FS_GCCFG)" ] pub fs_gccfg : FS_GCCFG , # [ doc = "0x3c - core ID register" ] pub fs_cid : FS_CID , _reserved2 : [ u8 ; 192usize ] , # [ doc = "0x100 - OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)" ] pub fs_hptxfsiz : FS_HPTXFSIZ , # [ doc = "0x104 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)" ] pub fs_dieptxf1 : FS_DIEPTXF1 , # [ doc = "0x108 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)" ] pub fs_dieptxf2 : FS_DIEPTXF2 , # [ doc = "0x10c - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)" ] pub fs_dieptxf3 : FS_DIEPTXF3 , }
+    pub struct RegisterBlock {
+        #[doc = "0x00 - OTG_FS control and status register (OTG_FS_GOTGCTL)"]
+        pub fs_gotgctl: FS_GOTGCTL,
+        #[doc = "0x04 - OTG_FS interrupt register (OTG_FS_GOTGINT)"]
+        pub fs_gotgint: FS_GOTGINT,
+        #[doc = "0x08 - OTG_FS AHB configuration register (OTG_FS_GAHBCFG)"]
+        pub fs_gahbcfg: FS_GAHBCFG,
+        #[doc = "0x0c - OTG_FS USB configuration register (OTG_FS_GUSBCFG)"]
+        pub fs_gusbcfg: FS_GUSBCFG,
+        #[doc = "0x10 - OTG_FS reset register (OTG_FS_GRSTCTL)"]
+        pub fs_grstctl: FS_GRSTCTL,
+        #[doc = "0x14 - OTG_FS core interrupt register (OTG_FS_GINTSTS)"]
+        pub fs_gintsts: FS_GINTSTS,
+        #[doc = "0x18 - OTG_FS interrupt mask register (OTG_FS_GINTMSK)"]
+        pub fs_gintmsk: FS_GINTMSK,
+        #[doc = "0x1c - OTG_FS Receive status debug read(Device mode)"]
+        pub fs_grxstsr_device: FS_GRXSTSR_DEVICE,
+        _reserved0: [u8; 4usize],
+        #[doc = "0x24 - OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)"]
+        pub fs_grxfsiz: FS_GRXFSIZ,
+        #[doc = "0x28 - OTG_FS non-periodic transmit FIFO size register (Device mode)"]
+        pub fs_gnptxfsiz_device: FS_GNPTXFSIZ_DEVICE,
+        #[doc = "0x2c - OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)"]
+        pub fs_gnptxsts: FS_GNPTXSTS,
+        _reserved1: [u8; 8usize],
+        #[doc = "0x38 - OTG_FS general core configuration register (OTG_FS_GCCFG)"]
+        pub fs_gccfg: FS_GCCFG,
+        #[doc = "0x3c - core ID register"]
+        pub fs_cid: FS_CID,
+        _reserved2: [u8; 192usize],
+        #[doc = "0x100 - OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)"]
+        pub fs_hptxfsiz: FS_HPTXFSIZ,
+        #[doc = "0x104 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)"]
+        pub fs_dieptxf1: FS_DIEPTXF1,
+        #[doc = "0x108 - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)"]
+        pub fs_dieptxf2: FS_DIEPTXF2,
+        #[doc = "0x10c - OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)"]
+        pub fs_dieptxf3: FS_DIEPTXF3,
+    }
     #[doc = "OTG_FS control and status register (OTG_FS_GOTGCTL)"]
     pub struct FS_GOTGCTL {
         register: VolatileCell<u32>,
@@ -313126,7 +313761,8 @@ pub mod otg_fs_global {
                 };
                 IISOIXFRR { bits }
             }
-            # [ doc = "Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)" ] # [ inline ]
+            #[doc = "Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)"]
+            #[inline]
             pub fn ipxfr_incompisoout(&self) -> IPXFR_INCOMPISOOUTR {
                 let bits = {
                     const MASK: bool = true;
@@ -313263,7 +313899,8 @@ pub mod otg_fs_global {
             pub fn iisoixfr(&mut self) -> _IISOIXFRW {
                 _IISOIXFRW { w: self }
             }
-            # [ doc = "Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)" ] # [ inline ]
+            #[doc = "Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)"]
+            #[inline]
             pub fn ipxfr_incompisoout(&mut self) -> _IPXFR_INCOMPISOOUTW {
                 _IPXFR_INCOMPISOOUTW { w: self }
             }
@@ -314592,7 +315229,8 @@ pub mod otg_fs_global {
                 };
                 IISOIXFRMR { bits }
             }
-            # [ doc = "Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)" ] # [ inline ]
+            #[doc = "Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)"]
+            #[inline]
             pub fn ipxfrm_iisooxfrm(&self) -> IPXFRM_IISOOXFRMR {
                 let bits = {
                     const MASK: bool = true;
@@ -314651,7 +315289,8 @@ pub mod otg_fs_global {
                 };
                 DISCINTR { bits }
             }
-            # [ doc = "Bit 30 - Session request/new session detected interrupt mask" ] # [ inline ]
+            #[doc = "Bit 30 - Session request/new session detected interrupt mask"]
+            #[inline]
             pub fn srqim(&self) -> SRQIMR {
                 let bits = {
                     const MASK: bool = true;
@@ -314768,7 +315407,8 @@ pub mod otg_fs_global {
             pub fn iisoixfrm(&mut self) -> _IISOIXFRMW {
                 _IISOIXFRMW { w: self }
             }
-            # [ doc = "Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)" ] # [ inline ]
+            #[doc = "Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)"]
+            #[inline]
             pub fn ipxfrm_iisooxfrm(&mut self) -> _IPXFRM_IISOOXFRMW {
                 _IPXFRM_IISOOXFRMW { w: self }
             }
@@ -314792,7 +315432,8 @@ pub mod otg_fs_global {
             pub fn discint(&mut self) -> _DISCINTW {
                 _DISCINTW { w: self }
             }
-            # [ doc = "Bit 30 - Session request/new session detected interrupt mask" ] # [ inline ]
+            #[doc = "Bit 30 - Session request/new session detected interrupt mask"]
+            #[inline]
             pub fn srqim(&mut self) -> _SRQIMW {
                 _SRQIMW { w: self }
             }
@@ -315485,11 +316126,11 @@ pub mod otg_fs_global {
             }
         }
     }
-    # [ doc = "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)" ]
+    #[doc = "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)"]
     pub struct FS_GNPTXSTS {
         register: VolatileCell<u32>,
     }
-    # [ doc = "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)" ]
+    #[doc = "OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)"]
     pub mod fs_gnptxsts {
         #[doc = r" Value read from the register"]
         pub struct R {
@@ -315553,7 +316194,8 @@ pub mod otg_fs_global {
                 };
                 NPTXFSAVR { bits }
             }
-            # [ doc = "Bits 16:23 - Non-periodic transmit request queue space available" ] # [ inline ]
+            #[doc = "Bits 16:23 - Non-periodic transmit request queue space available"]
+            #[inline]
             pub fn nptqxsav(&self) -> NPTQXSAVR {
                 let bits = {
                     const MASK: u8 = 0xff;
@@ -315562,7 +316204,8 @@ pub mod otg_fs_global {
                 };
                 NPTQXSAVR { bits }
             }
-            # [ doc = "Bits 24:30 - Top of the non-periodic transmit request queue" ] # [ inline ]
+            #[doc = "Bits 24:30 - Top of the non-periodic transmit request queue"]
+            #[inline]
             pub fn nptxqtop(&self) -> NPTXQTOPR {
                 let bits = {
                     const MASK: u8 = 0x7f;
@@ -316499,11 +317142,11 @@ pub mod otg_fs_global {
             }
         }
     }
-    # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)" ]
+    #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)"]
     pub struct FS_DIEPTXF1 {
         register: VolatileCell<u32>,
     }
-    # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)" ]
+    #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)"]
     pub mod fs_dieptxf1 {
         #[doc = r" Value read from the register"]
         pub struct R {
@@ -316652,11 +317295,11 @@ pub mod otg_fs_global {
             }
         }
     }
-    # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)" ]
+    #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)"]
     pub struct FS_DIEPTXF2 {
         register: VolatileCell<u32>,
     }
-    # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)" ]
+    #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)"]
     pub mod fs_dieptxf2 {
         #[doc = r" Value read from the register"]
         pub struct R {
@@ -316805,11 +317448,11 @@ pub mod otg_fs_global {
             }
         }
     }
-    # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)" ]
+    #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)"]
     pub struct FS_DIEPTXF3 {
         register: VolatileCell<u32>,
     }
-    # [ doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)" ]
+    #[doc = "OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)"]
     pub mod fs_dieptxf3 {
         #[doc = r" Value read from the register"]
         pub struct R {
@@ -316981,7 +317624,104 @@ pub mod otg_fs_host {
     use vcell::VolatileCell;
     #[doc = r" Register block"]
     #[repr(C)]
-    pub struct RegisterBlock { # [ doc = "0x00 - OTG_FS host configuration register (OTG_FS_HCFG)" ] pub fs_hcfg : FS_HCFG , # [ doc = "0x04 - OTG_FS Host frame interval register" ] pub hfir : HFIR , # [ doc = "0x08 - OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)" ] pub fs_hfnum : FS_HFNUM , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x10 - OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)" ] pub fs_hptxsts : FS_HPTXSTS , # [ doc = "0x14 - OTG_FS Host all channels interrupt register" ] pub haint : HAINT , # [ doc = "0x18 - OTG_FS host all channels interrupt mask register" ] pub haintmsk : HAINTMSK , _reserved1 : [ u8 ; 36usize ] , # [ doc = "0x40 - OTG_FS host port control and status register (OTG_FS_HPRT)" ] pub fs_hprt : FS_HPRT , _reserved2 : [ u8 ; 188usize ] , # [ doc = "0x100 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)" ] pub fs_hcchar0 : FS_HCCHAR0 , _reserved3 : [ u8 ; 4usize ] , # [ doc = "0x108 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)" ] pub fs_hcint0 : FS_HCINT0 , # [ doc = "0x10c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)" ] pub fs_hcintmsk0 : FS_HCINTMSK0 , # [ doc = "0x110 - OTG_FS host channel-0 transfer size register" ] pub fs_hctsiz0 : FS_HCTSIZ0 , _reserved4 : [ u8 ; 12usize ] , # [ doc = "0x120 - OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)" ] pub fs_hcchar1 : FS_HCCHAR1 , _reserved5 : [ u8 ; 4usize ] , # [ doc = "0x128 - OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)" ] pub fs_hcint1 : FS_HCINT1 , # [ doc = "0x12c - OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)" ] pub fs_hcintmsk1 : FS_HCINTMSK1 , # [ doc = "0x130 - OTG_FS host channel-1 transfer size register" ] pub fs_hctsiz1 : FS_HCTSIZ1 , _reserved6 : [ u8 ; 12usize ] , # [ doc = "0x140 - OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)" ] pub fs_hcchar2 : FS_HCCHAR2 , _reserved7 : [ u8 ; 4usize ] , # [ doc = "0x148 - OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)" ] pub fs_hcint2 : FS_HCINT2 , # [ doc = "0x14c - OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)" ] pub fs_hcintmsk2 : FS_HCINTMSK2 , # [ doc = "0x150 - OTG_FS host channel-2 transfer size register" ] pub fs_hctsiz2 : FS_HCTSIZ2 , _reserved8 : [ u8 ; 12usize ] , # [ doc = "0x160 - OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)" ] pub fs_hcchar3 : FS_HCCHAR3 , _reserved9 : [ u8 ; 4usize ] , # [ doc = "0x168 - OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)" ] pub fs_hcint3 : FS_HCINT3 , # [ doc = "0x16c - OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)" ] pub fs_hcintmsk3 : FS_HCINTMSK3 , # [ doc = "0x170 - OTG_FS host channel-3 transfer size register" ] pub fs_hctsiz3 : FS_HCTSIZ3 , _reserved10 : [ u8 ; 12usize ] , # [ doc = "0x180 - OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)" ] pub fs_hcchar4 : FS_HCCHAR4 , _reserved11 : [ u8 ; 4usize ] , # [ doc = "0x188 - OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)" ] pub fs_hcint4 : FS_HCINT4 , # [ doc = "0x18c - OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)" ] pub fs_hcintmsk4 : FS_HCINTMSK4 , # [ doc = "0x190 - OTG_FS host channel-x transfer size register" ] pub fs_hctsiz4 : FS_HCTSIZ4 , _reserved12 : [ u8 ; 12usize ] , # [ doc = "0x1a0 - OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)" ] pub fs_hcchar5 : FS_HCCHAR5 , _reserved13 : [ u8 ; 4usize ] , # [ doc = "0x1a8 - OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)" ] pub fs_hcint5 : FS_HCINT5 , # [ doc = "0x1ac - OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)" ] pub fs_hcintmsk5 : FS_HCINTMSK5 , # [ doc = "0x1b0 - OTG_FS host channel-5 transfer size register" ] pub fs_hctsiz5 : FS_HCTSIZ5 , _reserved14 : [ u8 ; 12usize ] , # [ doc = "0x1c0 - OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)" ] pub fs_hcchar6 : FS_HCCHAR6 , _reserved15 : [ u8 ; 4usize ] , # [ doc = "0x1c8 - OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)" ] pub fs_hcint6 : FS_HCINT6 , # [ doc = "0x1cc - OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)" ] pub fs_hcintmsk6 : FS_HCINTMSK6 , # [ doc = "0x1d0 - OTG_FS host channel-6 transfer size register" ] pub fs_hctsiz6 : FS_HCTSIZ6 , _reserved16 : [ u8 ; 12usize ] , # [ doc = "0x1e0 - OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)" ] pub fs_hcchar7 : FS_HCCHAR7 , _reserved17 : [ u8 ; 4usize ] , # [ doc = "0x1e8 - OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)" ] pub fs_hcint7 : FS_HCINT7 , # [ doc = "0x1ec - OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)" ] pub fs_hcintmsk7 : FS_HCINTMSK7 , # [ doc = "0x1f0 - OTG_FS host channel-7 transfer size register" ] pub fs_hctsiz7 : FS_HCTSIZ7 , }
+    pub struct RegisterBlock {
+        #[doc = "0x00 - OTG_FS host configuration register (OTG_FS_HCFG)"]
+        pub fs_hcfg: FS_HCFG,
+        #[doc = "0x04 - OTG_FS Host frame interval register"]
+        pub hfir: HFIR,
+        #[doc = "0x08 - OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)"]
+        pub fs_hfnum: FS_HFNUM,
+        _reserved0: [u8; 4usize],
+        #[doc = "0x10 - OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)"]
+        pub fs_hptxsts: FS_HPTXSTS,
+        #[doc = "0x14 - OTG_FS Host all channels interrupt register"]
+        pub haint: HAINT,
+        #[doc = "0x18 - OTG_FS host all channels interrupt mask register"]
+        pub haintmsk: HAINTMSK,
+        _reserved1: [u8; 36usize],
+        #[doc = "0x40 - OTG_FS host port control and status register (OTG_FS_HPRT)"]
+        pub fs_hprt: FS_HPRT,
+        _reserved2: [u8; 188usize],
+        #[doc = "0x100 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)"]
+        pub fs_hcchar0: FS_HCCHAR0,
+        _reserved3: [u8; 4usize],
+        #[doc = "0x108 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)"]
+        pub fs_hcint0: FS_HCINT0,
+        #[doc = "0x10c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)"]
+        pub fs_hcintmsk0: FS_HCINTMSK0,
+        #[doc = "0x110 - OTG_FS host channel-0 transfer size register"]
+        pub fs_hctsiz0: FS_HCTSIZ0,
+        _reserved4: [u8; 12usize],
+        #[doc = "0x120 - OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)"]
+        pub fs_hcchar1: FS_HCCHAR1,
+        _reserved5: [u8; 4usize],
+        #[doc = "0x128 - OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)"]
+        pub fs_hcint1: FS_HCINT1,
+        #[doc = "0x12c - OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)"]
+        pub fs_hcintmsk1: FS_HCINTMSK1,
+        #[doc = "0x130 - OTG_FS host channel-1 transfer size register"]
+        pub fs_hctsiz1: FS_HCTSIZ1,
+        _reserved6: [u8; 12usize],
+        #[doc = "0x140 - OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)"]
+        pub fs_hcchar2: FS_HCCHAR2,
+        _reserved7: [u8; 4usize],
+        #[doc = "0x148 - OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)"]
+        pub fs_hcint2: FS_HCINT2,
+        #[doc = "0x14c - OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)"]
+        pub fs_hcintmsk2: FS_HCINTMSK2,
+        #[doc = "0x150 - OTG_FS host channel-2 transfer size register"]
+        pub fs_hctsiz2: FS_HCTSIZ2,
+        _reserved8: [u8; 12usize],
+        #[doc = "0x160 - OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)"]
+        pub fs_hcchar3: FS_HCCHAR3,
+        _reserved9: [u8; 4usize],
+        #[doc = "0x168 - OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)"]
+        pub fs_hcint3: FS_HCINT3,
+        #[doc = "0x16c - OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)"]
+        pub fs_hcintmsk3: FS_HCINTMSK3,
+        #[doc = "0x170 - OTG_FS host channel-3 transfer size register"]
+        pub fs_hctsiz3: FS_HCTSIZ3,
+        _reserved10: [u8; 12usize],
+        #[doc = "0x180 - OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)"]
+        pub fs_hcchar4: FS_HCCHAR4,
+        _reserved11: [u8; 4usize],
+        #[doc = "0x188 - OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)"]
+        pub fs_hcint4: FS_HCINT4,
+        #[doc = "0x18c - OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)"]
+        pub fs_hcintmsk4: FS_HCINTMSK4,
+        #[doc = "0x190 - OTG_FS host channel-x transfer size register"]
+        pub fs_hctsiz4: FS_HCTSIZ4,
+        _reserved12: [u8; 12usize],
+        #[doc = "0x1a0 - OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)"]
+        pub fs_hcchar5: FS_HCCHAR5,
+        _reserved13: [u8; 4usize],
+        #[doc = "0x1a8 - OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)"]
+        pub fs_hcint5: FS_HCINT5,
+        #[doc = "0x1ac - OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)"]
+        pub fs_hcintmsk5: FS_HCINTMSK5,
+        #[doc = "0x1b0 - OTG_FS host channel-5 transfer size register"]
+        pub fs_hctsiz5: FS_HCTSIZ5,
+        _reserved14: [u8; 12usize],
+        #[doc = "0x1c0 - OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)"]
+        pub fs_hcchar6: FS_HCCHAR6,
+        _reserved15: [u8; 4usize],
+        #[doc = "0x1c8 - OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)"]
+        pub fs_hcint6: FS_HCINT6,
+        #[doc = "0x1cc - OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)"]
+        pub fs_hcintmsk6: FS_HCINTMSK6,
+        #[doc = "0x1d0 - OTG_FS host channel-6 transfer size register"]
+        pub fs_hctsiz6: FS_HCTSIZ6,
+        _reserved16: [u8; 12usize],
+        #[doc = "0x1e0 - OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)"]
+        pub fs_hcchar7: FS_HCCHAR7,
+        _reserved17: [u8; 4usize],
+        #[doc = "0x1e8 - OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)"]
+        pub fs_hcint7: FS_HCINT7,
+        #[doc = "0x1ec - OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)"]
+        pub fs_hcintmsk7: FS_HCINTMSK7,
+        #[doc = "0x1f0 - OTG_FS host channel-7 transfer size register"]
+        pub fs_hctsiz7: FS_HCTSIZ7,
+    }
     #[doc = "OTG_FS host configuration register (OTG_FS_HCFG)"]
     pub struct FS_HCFG {
         register: VolatileCell<u32>,
@@ -317237,11 +317977,11 @@ pub mod otg_fs_host {
             }
         }
     }
-    # [ doc = "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)" ]
+    #[doc = "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)"]
     pub struct FS_HFNUM {
         register: VolatileCell<u32>,
     }
-    # [ doc = "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)" ]
+    #[doc = "OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)"]
     pub mod fs_hfnum {
         #[doc = r" Value read from the register"]
         pub struct R {
@@ -317306,11 +318046,11 @@ pub mod otg_fs_host {
             }
         }
     }
-    # [ doc = "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)" ]
+    #[doc = "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)"]
     pub struct FS_HPTXSTS {
         register: VolatileCell<u32>,
     }
-    # [ doc = "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)" ]
+    #[doc = "OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)"]
     pub mod fs_hptxsts {
         #[doc = r" Value read from the register"]
         pub struct R {
@@ -317420,7 +318160,8 @@ pub mod otg_fs_host {
                 };
                 PTXFSAVLR { bits }
             }
-            # [ doc = "Bits 16:23 - Periodic transmit request queue space available" ] # [ inline ]
+            #[doc = "Bits 16:23 - Periodic transmit request queue space available"]
+            #[inline]
             pub fn ptxqsav(&self) -> PTXQSAVR {
                 let bits = {
                     const MASK: u8 = 0xff;
@@ -334554,7 +335295,115 @@ pub mod otg_fs_device {
     use vcell::VolatileCell;
     #[doc = r" Register block"]
     #[repr(C)]
-    pub struct RegisterBlock { # [ doc = "0x00 - OTG_FS device configuration register (OTG_FS_DCFG)" ] pub fs_dcfg : FS_DCFG , # [ doc = "0x04 - OTG_FS device control register (OTG_FS_DCTL)" ] pub fs_dctl : FS_DCTL , # [ doc = "0x08 - OTG_FS device status register (OTG_FS_DSTS)" ] pub fs_dsts : FS_DSTS , _reserved0 : [ u8 ; 4usize ] , # [ doc = "0x10 - OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)" ] pub fs_diepmsk : FS_DIEPMSK , # [ doc = "0x14 - OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)" ] pub fs_doepmsk : FS_DOEPMSK , # [ doc = "0x18 - OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)" ] pub fs_daint : FS_DAINT , # [ doc = "0x1c - OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)" ] pub fs_daintmsk : FS_DAINTMSK , _reserved1 : [ u8 ; 8usize ] , # [ doc = "0x28 - OTG_FS device VBUS discharge time register" ] pub dvbusdis : DVBUSDIS , # [ doc = "0x2c - OTG_FS device VBUS pulsing time register" ] pub dvbuspulse : DVBUSPULSE , _reserved2 : [ u8 ; 4usize ] , # [ doc = "0x34 - OTG_FS device IN endpoint FIFO empty interrupt mask register" ] pub diepempmsk : DIEPEMPMSK , _reserved3 : [ u8 ; 200usize ] , # [ doc = "0x100 - OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)" ] pub fs_diepctl0 : FS_DIEPCTL0 , _reserved4 : [ u8 ; 4usize ] , # [ doc = "0x108 - device endpoint-x interrupt register" ] pub diepint0 : DIEPINT0 , _reserved5 : [ u8 ; 4usize ] , # [ doc = "0x110 - device endpoint-0 transfer size register" ] pub dieptsiz0 : DIEPTSIZ0 , _reserved6 : [ u8 ; 4usize ] , # [ doc = "0x118 - OTG_FS device IN endpoint transmit FIFO status register" ] pub dtxfsts0 : DTXFSTS0 , _reserved7 : [ u8 ; 4usize ] , # [ doc = "0x120 - OTG device endpoint-1 control register" ] pub diepctl1 : DIEPCTL1 , _reserved8 : [ u8 ; 4usize ] , # [ doc = "0x128 - device endpoint-1 interrupt register" ] pub diepint1 : DIEPINT1 , _reserved9 : [ u8 ; 4usize ] , # [ doc = "0x130 - device endpoint-1 transfer size register" ] pub dieptsiz1 : DIEPTSIZ1 , _reserved10 : [ u8 ; 4usize ] , # [ doc = "0x138 - OTG_FS device IN endpoint transmit FIFO status register" ] pub dtxfsts1 : DTXFSTS1 , _reserved11 : [ u8 ; 4usize ] , # [ doc = "0x140 - OTG device endpoint-2 control register" ] pub diepctl2 : DIEPCTL2 , _reserved12 : [ u8 ; 4usize ] , # [ doc = "0x148 - device endpoint-2 interrupt register" ] pub diepint2 : DIEPINT2 , _reserved13 : [ u8 ; 4usize ] , # [ doc = "0x150 - device endpoint-2 transfer size register" ] pub dieptsiz2 : DIEPTSIZ2 , _reserved14 : [ u8 ; 4usize ] , # [ doc = "0x158 - OTG_FS device IN endpoint transmit FIFO status register" ] pub dtxfsts2 : DTXFSTS2 , _reserved15 : [ u8 ; 4usize ] , # [ doc = "0x160 - OTG device endpoint-3 control register" ] pub diepctl3 : DIEPCTL3 , _reserved16 : [ u8 ; 4usize ] , # [ doc = "0x168 - device endpoint-3 interrupt register" ] pub diepint3 : DIEPINT3 , _reserved17 : [ u8 ; 4usize ] , # [ doc = "0x170 - device endpoint-3 transfer size register" ] pub dieptsiz3 : DIEPTSIZ3 , _reserved18 : [ u8 ; 4usize ] , # [ doc = "0x178 - OTG_FS device IN endpoint transmit FIFO status register" ] pub dtxfsts3 : DTXFSTS3 , _reserved19 : [ u8 ; 388usize ] , # [ doc = "0x300 - device endpoint-0 control register" ] pub doepctl0 : DOEPCTL0 , _reserved20 : [ u8 ; 4usize ] , # [ doc = "0x308 - device endpoint-0 interrupt register" ] pub doepint0 : DOEPINT0 , _reserved21 : [ u8 ; 4usize ] , # [ doc = "0x310 - device OUT endpoint-0 transfer size register" ] pub doeptsiz0 : DOEPTSIZ0 , _reserved22 : [ u8 ; 12usize ] , # [ doc = "0x320 - device endpoint-1 control register" ] pub doepctl1 : DOEPCTL1 , _reserved23 : [ u8 ; 4usize ] , # [ doc = "0x328 - device endpoint-1 interrupt register" ] pub doepint1 : DOEPINT1 , _reserved24 : [ u8 ; 4usize ] , # [ doc = "0x330 - device OUT endpoint-1 transfer size register" ] pub doeptsiz1 : DOEPTSIZ1 , _reserved25 : [ u8 ; 12usize ] , # [ doc = "0x340 - device endpoint-2 control register" ] pub doepctl2 : DOEPCTL2 , _reserved26 : [ u8 ; 4usize ] , # [ doc = "0x348 - device endpoint-2 interrupt register" ] pub doepint2 : DOEPINT2 , _reserved27 : [ u8 ; 4usize ] , # [ doc = "0x350 - device OUT endpoint-2 transfer size register" ] pub doeptsiz2 : DOEPTSIZ2 , _reserved28 : [ u8 ; 12usize ] , # [ doc = "0x360 - device endpoint-3 control register" ] pub doepctl3 : DOEPCTL3 , _reserved29 : [ u8 ; 4usize ] , # [ doc = "0x368 - device endpoint-3 interrupt register" ] pub doepint3 : DOEPINT3 , _reserved30 : [ u8 ; 4usize ] , # [ doc = "0x370 - device OUT endpoint-3 transfer size register" ] pub doeptsiz3 : DOEPTSIZ3 , }
+    pub struct RegisterBlock {
+        #[doc = "0x00 - OTG_FS device configuration register (OTG_FS_DCFG)"]
+        pub fs_dcfg: FS_DCFG,
+        #[doc = "0x04 - OTG_FS device control register (OTG_FS_DCTL)"]
+        pub fs_dctl: FS_DCTL,
+        #[doc = "0x08 - OTG_FS device status register (OTG_FS_DSTS)"]
+        pub fs_dsts: FS_DSTS,
+        _reserved0: [u8; 4usize],
+        #[doc = "0x10 - OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)"]
+        pub fs_diepmsk: FS_DIEPMSK,
+        #[doc = "0x14 - OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)"]
+        pub fs_doepmsk: FS_DOEPMSK,
+        #[doc = "0x18 - OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)"]
+        pub fs_daint: FS_DAINT,
+        #[doc = "0x1c - OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)"]
+        pub fs_daintmsk: FS_DAINTMSK,
+        _reserved1: [u8; 8usize],
+        #[doc = "0x28 - OTG_FS device VBUS discharge time register"]
+        pub dvbusdis: DVBUSDIS,
+        #[doc = "0x2c - OTG_FS device VBUS pulsing time register"]
+        pub dvbuspulse: DVBUSPULSE,
+        _reserved2: [u8; 4usize],
+        #[doc = "0x34 - OTG_FS device IN endpoint FIFO empty interrupt mask register"]
+        pub diepempmsk: DIEPEMPMSK,
+        _reserved3: [u8; 200usize],
+        #[doc = "0x100 - OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)"]
+        pub fs_diepctl0: FS_DIEPCTL0,
+        _reserved4: [u8; 4usize],
+        #[doc = "0x108 - device endpoint-x interrupt register"]
+        pub diepint0: DIEPINT0,
+        _reserved5: [u8; 4usize],
+        #[doc = "0x110 - device endpoint-0 transfer size register"]
+        pub dieptsiz0: DIEPTSIZ0,
+        _reserved6: [u8; 4usize],
+        #[doc = "0x118 - OTG_FS device IN endpoint transmit FIFO status register"]
+        pub dtxfsts0: DTXFSTS0,
+        _reserved7: [u8; 4usize],
+        #[doc = "0x120 - OTG device endpoint-1 control register"]
+        pub diepctl1: DIEPCTL1,
+        _reserved8: [u8; 4usize],
+        #[doc = "0x128 - device endpoint-1 interrupt register"]
+        pub diepint1: DIEPINT1,
+        _reserved9: [u8; 4usize],
+        #[doc = "0x130 - device endpoint-1 transfer size register"]
+        pub dieptsiz1: DIEPTSIZ1,
+        _reserved10: [u8; 4usize],
+        #[doc = "0x138 - OTG_FS device IN endpoint transmit FIFO status register"]
+        pub dtxfsts1: DTXFSTS1,
+        _reserved11: [u8; 4usize],
+        #[doc = "0x140 - OTG device endpoint-2 control register"]
+        pub diepctl2: DIEPCTL2,
+        _reserved12: [u8; 4usize],
+        #[doc = "0x148 - device endpoint-2 interrupt register"]
+        pub diepint2: DIEPINT2,
+        _reserved13: [u8; 4usize],
+        #[doc = "0x150 - device endpoint-2 transfer size register"]
+        pub dieptsiz2: DIEPTSIZ2,
+        _reserved14: [u8; 4usize],
+        #[doc = "0x158 - OTG_FS device IN endpoint transmit FIFO status register"]
+        pub dtxfsts2: DTXFSTS2,
+        _reserved15: [u8; 4usize],
+        #[doc = "0x160 - OTG device endpoint-3 control register"]
+        pub diepctl3: DIEPCTL3,
+        _reserved16: [u8; 4usize],
+        #[doc = "0x168 - device endpoint-3 interrupt register"]
+        pub diepint3: DIEPINT3,
+        _reserved17: [u8; 4usize],
+        #[doc = "0x170 - device endpoint-3 transfer size register"]
+        pub dieptsiz3: DIEPTSIZ3,
+        _reserved18: [u8; 4usize],
+        #[doc = "0x178 - OTG_FS device IN endpoint transmit FIFO status register"]
+        pub dtxfsts3: DTXFSTS3,
+        _reserved19: [u8; 388usize],
+        #[doc = "0x300 - device endpoint-0 control register"]
+        pub doepctl0: DOEPCTL0,
+        _reserved20: [u8; 4usize],
+        #[doc = "0x308 - device endpoint-0 interrupt register"]
+        pub doepint0: DOEPINT0,
+        _reserved21: [u8; 4usize],
+        #[doc = "0x310 - device OUT endpoint-0 transfer size register"]
+        pub doeptsiz0: DOEPTSIZ0,
+        _reserved22: [u8; 12usize],
+        #[doc = "0x320 - device endpoint-1 control register"]
+        pub doepctl1: DOEPCTL1,
+        _reserved23: [u8; 4usize],
+        #[doc = "0x328 - device endpoint-1 interrupt register"]
+        pub doepint1: DOEPINT1,
+        _reserved24: [u8; 4usize],
+        #[doc = "0x330 - device OUT endpoint-1 transfer size register"]
+        pub doeptsiz1: DOEPTSIZ1,
+        _reserved25: [u8; 12usize],
+        #[doc = "0x340 - device endpoint-2 control register"]
+        pub doepctl2: DOEPCTL2,
+        _reserved26: [u8; 4usize],
+        #[doc = "0x348 - device endpoint-2 interrupt register"]
+        pub doepint2: DOEPINT2,
+        _reserved27: [u8; 4usize],
+        #[doc = "0x350 - device OUT endpoint-2 transfer size register"]
+        pub doeptsiz2: DOEPTSIZ2,
+        _reserved28: [u8; 12usize],
+        #[doc = "0x360 - device endpoint-3 control register"]
+        pub doepctl3: DOEPCTL3,
+        _reserved29: [u8; 4usize],
+        #[doc = "0x368 - device endpoint-3 interrupt register"]
+        pub doepint3: DOEPINT3,
+        _reserved30: [u8; 4usize],
+        #[doc = "0x370 - device OUT endpoint-3 transfer size register"]
+        pub doeptsiz3: DOEPTSIZ3,
+    }
     #[doc = "OTG_FS device configuration register (OTG_FS_DCFG)"]
     pub struct FS_DCFG {
         register: VolatileCell<u32>,
@@ -335547,11 +336396,11 @@ pub mod otg_fs_device {
             }
         }
     }
-    # [ doc = "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)" ]
+    #[doc = "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)"]
     pub struct FS_DIEPMSK {
         register: VolatileCell<u32>,
     }
-    # [ doc = "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)" ]
+    #[doc = "OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)"]
     pub mod fs_diepmsk {
         #[doc = r" Value read from the register"]
         pub struct R {
@@ -335972,11 +336821,11 @@ pub mod otg_fs_device {
             }
         }
     }
-    # [ doc = "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)" ]
+    #[doc = "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)"]
     pub struct FS_DOEPMSK {
         register: VolatileCell<u32>,
     }
-    # [ doc = "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)" ]
+    #[doc = "OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)"]
     pub mod fs_doepmsk {
         #[doc = r" Value read from the register"]
         pub struct R {
@@ -336837,11 +337686,11 @@ pub mod otg_fs_device {
             }
         }
     }
-    # [ doc = "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)" ]
+    #[doc = "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)"]
     pub struct FS_DIEPCTL0 {
         register: VolatileCell<u32>,
     }
-    # [ doc = "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)" ]
+    #[doc = "OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)"]
     pub mod fs_diepctl0 {
         #[doc = r" Value read from the register"]
         pub struct R {
@@ -346132,7 +346981,10 @@ pub mod otg_fs_pwrclk {
     use vcell::VolatileCell;
     #[doc = r" Register block"]
     #[repr(C)]
-    pub struct RegisterBlock { # [ doc = "0x00 - OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)" ] pub fs_pcgcctl : FS_PCGCCTL , }
+    pub struct RegisterBlock {
+        #[doc = "0x00 - OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)"]
+        pub fs_pcgcctl: FS_PCGCCTL,
+    }
     #[doc = "OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)"]
     pub struct FS_PCGCCTL {
         register: VolatileCell<u32>,
@@ -352663,7 +353515,8 @@ pub mod dac {
                 };
                 MAMP2R { bits }
             }
-            # [ doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable" ] # [ inline ]
+            #[doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable"]
+            #[inline]
             pub fn wave2(&self) -> WAVE2R {
                 let bits = {
                     const MASK: u8 = 0x03;
@@ -352742,7 +353595,8 @@ pub mod dac {
                 };
                 MAMP1R { bits }
             }
-            # [ doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable" ] # [ inline ]
+            #[doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable"]
+            #[inline]
             pub fn wave1(&self) -> WAVE1R {
                 let bits = {
                     const MASK: u8 = 0x03;
@@ -352819,7 +353673,8 @@ pub mod dac {
             pub fn mamp2(&mut self) -> _MAMP2W {
                 _MAMP2W { w: self }
             }
-            # [ doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable" ] # [ inline ]
+            #[doc = "Bits 22:23 - DAC channel2 noise/triangle wave generation enable"]
+            #[inline]
             pub fn wave2(&mut self) -> _WAVE2W {
                 _WAVE2W { w: self }
             }
@@ -352858,7 +353713,8 @@ pub mod dac {
             pub fn mamp1(&mut self) -> _MAMP1W {
                 _MAMP1W { w: self }
             }
-            # [ doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable" ] # [ inline ]
+            #[doc = "Bits 6:7 - DAC channel1 noise/triangle wave generation enable"]
+            #[inline]
             pub fn wave1(&mut self) -> _WAVE1W {
                 _WAVE1W { w: self }
             }
@@ -356557,7 +357413,8 @@ pub mod sai {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bit 6 - Late frame synchronization detection interrupt enable" ] # [ inline ]
+            #[doc = "Bit 6 - Late frame synchronization detection interrupt enable"]
+            #[inline]
             pub fn lfsdetie(&self) -> LFSDETIER {
                 let bits = {
                     const MASK: bool = true;
@@ -356566,7 +357423,8 @@ pub mod sai {
                 };
                 LFSDETIER { bits }
             }
-            # [ doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable" ] # [ inline ]
+            #[doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable"]
+            #[inline]
             pub fn afsdetie(&self) -> AFSDETIER {
                 let bits = {
                     const MASK: bool = true;
@@ -356638,11 +357496,13 @@ pub mod sai {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bit 6 - Late frame synchronization detection interrupt enable" ] # [ inline ]
+            #[doc = "Bit 6 - Late frame synchronization detection interrupt enable"]
+            #[inline]
             pub fn lfsdetie(&mut self) -> _LFSDETIEW {
                 _LFSDETIEW { w: self }
             }
-            # [ doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable" ] # [ inline ]
+            #[doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable"]
+            #[inline]
             pub fn afsdetie(&mut self) -> _AFSDETIEW {
                 _AFSDETIEW { w: self }
             }
@@ -357115,7 +357975,8 @@ pub mod sai {
             pub fn lfsdet(&mut self) -> _LFSDETW {
                 _LFSDETW { w: self }
             }
-            # [ doc = "Bit 5 - Clear anticipated frame synchronization detection flag" ] # [ inline ]
+            #[doc = "Bit 5 - Clear anticipated frame synchronization detection flag"]
+            #[inline]
             pub fn cafsdet(&mut self) -> _CAFSDETW {
                 _CAFSDETW { w: self }
             }
@@ -359360,7 +360221,8 @@ pub mod sai {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bit 6 - Late frame synchronization detection interrupt enable" ] # [ inline ]
+            #[doc = "Bit 6 - Late frame synchronization detection interrupt enable"]
+            #[inline]
             pub fn lfsdet(&self) -> LFSDETR {
                 let bits = {
                     const MASK: bool = true;
@@ -359369,7 +360231,8 @@ pub mod sai {
                 };
                 LFSDETR { bits }
             }
-            # [ doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable" ] # [ inline ]
+            #[doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable"]
+            #[inline]
             pub fn afsdetie(&self) -> AFSDETIER {
                 let bits = {
                     const MASK: bool = true;
@@ -359441,11 +360304,13 @@ pub mod sai {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bit 6 - Late frame synchronization detection interrupt enable" ] # [ inline ]
+            #[doc = "Bit 6 - Late frame synchronization detection interrupt enable"]
+            #[inline]
             pub fn lfsdet(&mut self) -> _LFSDETW {
                 _LFSDETW { w: self }
             }
-            # [ doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable" ] # [ inline ]
+            #[doc = "Bit 5 - Anticipated frame synchronization detection interrupt enable"]
+            #[inline]
             pub fn afsdetie(&mut self) -> _AFSDETIEW {
                 _AFSDETIEW { w: self }
             }
@@ -359916,7 +360781,8 @@ pub mod sai {
                 };
                 FREQR { bits }
             }
-            # [ doc = "Bit 2 - Wrong clock configuration flag. This bit is read only." ] # [ inline ]
+            #[doc = "Bit 2 - Wrong clock configuration flag. This bit is read only."]
+            #[inline]
             pub fn wckcfg(&self) -> WCKCFGR {
                 let bits = {
                     const MASK: bool = true;
@@ -359983,7 +360849,8 @@ pub mod sai {
             pub fn freq(&mut self) -> _FREQW {
                 _FREQW { w: self }
             }
-            # [ doc = "Bit 2 - Wrong clock configuration flag. This bit is read only." ] # [ inline ]
+            #[doc = "Bit 2 - Wrong clock configuration flag. This bit is read only."]
+            #[inline]
             pub fn wckcfg(&mut self) -> _WCKCFGW {
                 _WCKCFGW { w: self }
             }
@@ -360329,7 +361196,8 @@ pub mod sai {
                 };
                 LFSDETR { bits }
             }
-            # [ doc = "Bit 5 - Clear anticipated frame synchronization detection flag." ] # [ inline ]
+            #[doc = "Bit 5 - Clear anticipated frame synchronization detection flag."]
+            #[inline]
             pub fn cafsdet(&self) -> CAFSDETR {
                 let bits = {
                     const MASK: bool = true;
@@ -360396,7 +361264,8 @@ pub mod sai {
             pub fn lfsdet(&mut self) -> _LFSDETW {
                 _LFSDETW { w: self }
             }
-            # [ doc = "Bit 5 - Clear anticipated frame synchronization detection flag." ] # [ inline ]
+            #[doc = "Bit 5 - Clear anticipated frame synchronization detection flag."]
+            #[inline]
             pub fn cafsdet(&mut self) -> _CAFSDETW {
                 _CAFSDETW { w: self }
             }
@@ -361105,7 +361974,8 @@ pub mod aes {
                 };
                 MODER { bits }
             }
-            # [ doc = "Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)" ] # [ inline ]
+            #[doc = "Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)"]
+            #[inline]
             pub fn datatype(&self) -> DATATYPER {
                 let bits = {
                     const MASK: u8 = 0x03;
@@ -361177,7 +362047,8 @@ pub mod aes {
             pub fn mode(&mut self) -> _MODEW {
                 _MODEW { w: self }
             }
-            # [ doc = "Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)" ] # [ inline ]
+            #[doc = "Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)"]
+            #[inline]
             pub fn datatype(&mut self) -> _DATATYPEW {
                 _DATATYPEW { w: self }
             }
@@ -361998,7 +362869,8 @@ pub mod aes {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:31 - initialization vector register (LSB IVR [31:0])" ] # [ inline ]
+            #[doc = "Bits 0:31 - initialization vector register (LSB IVR [31:0])"]
+            #[inline]
             pub fn aes_ivr0(&self) -> AES_IVR0R {
                 let bits = {
                     const MASK: u32 = 0xffff_ffff;
@@ -362020,7 +362892,8 @@ pub mod aes {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:31 - initialization vector register (LSB IVR [31:0])" ] # [ inline ]
+            #[doc = "Bits 0:31 - initialization vector register (LSB IVR [31:0])"]
+            #[inline]
             pub fn aes_ivr0(&mut self) -> _AES_IVR0W {
                 _AES_IVR0W { w: self }
             }
@@ -362332,7 +363205,8 @@ pub mod aes {
             pub fn bits(&self) -> u32 {
                 self.bits
             }
-            # [ doc = "Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])" ] # [ inline ]
+            #[doc = "Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])"]
+            #[inline]
             pub fn aes_ivr3(&self) -> AES_IVR3R {
                 let bits = {
                     const MASK: u32 = 0xffff_ffff;
@@ -362354,7 +363228,8 @@ pub mod aes {
                 self.bits = bits;
                 self
             }
-            # [ doc = "Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])" ] # [ inline ]
+            #[doc = "Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])"]
+            #[inline]
             pub fn aes_ivr3(&mut self) -> _AES_IVR3W {
                 _AES_IVR3W { w: self }
             }
-- 
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