From ed3e219861c9790944fbe2b8a9643599c09adf0d Mon Sep 17 00:00:00 2001
From: Per Lindgren <per.lindgren@ltu.se>
Date: Thu, 8 Feb 2018 14:09:32 +0100
Subject: [PATCH] traits work
---
examples/serial-dma-tx.rs | 2 +-
src/dma.rs | 35 ++++++++++++++++++++++++++++-------
src/serial.rs | 24 +++++++++++-------------
3 files changed, 40 insertions(+), 21 deletions(-)
diff --git a/examples/serial-dma-tx.rs b/examples/serial-dma-tx.rs
index 60fdba1..f9087ae 100644
--- a/examples/serial-dma-tx.rs
+++ b/examples/serial-dma-tx.rs
@@ -19,7 +19,7 @@ fn main() {
let mut rcc = p.RCC.constrain();
let mut gpioa = p.GPIOA.split(&mut rcc.ahb1);
let streams = p.DMA1.split(&mut rcc.ahb1);
- let tx_stream = streams.1.into_channel4(); // actually 5
+ let tx_stream = streams.1.into_channel4(); // S5<C4>
let clocks = rcc.cfgr.freeze(&mut flash.acr);
diff --git a/src/dma.rs b/src/dma.rs
index 24d436d..26967c4 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -7,6 +7,7 @@ use core::ops;
use rcc::AHB1;
use stm32f4x::USART2;
+use stm32f4x::{DMA1, dma2};
#[derive(Debug)]
pub enum Error {
@@ -66,6 +67,26 @@ pub trait DmaExt {
fn split(self, ahb: &mut AHB1) -> Self::Streams;
}
+pub trait Dma {
+ // sXcr stream x configuration register
+ fn cr(&mut self) -> &dma2::S5CR;
+
+ // sXfcr stream x FIFO control register
+ fn fcr(&mut self) -> &dma2::S5FCR;
+
+ // sXm0ar stream x memory 0 address register
+ fn m0ar(&mut self) -> &dma2::S5M0AR;
+
+ // sXm1ar stream x memory 0 address register
+ fn m1ar(&mut self) -> &dma2::S5M1AR;
+
+ // sXndtr stream x number of data register
+ fn ndtr(&mut self) -> &dma2::S5NDTR;
+
+ // sXpar stream x peripheral address register
+ fn par(&mut self) -> &dma2::S5PAR;
+}
+
pub struct Transfer<MODE, BUFFER, STREAM, PAYLOAD> {
_mode: PhantomData<MODE>,
buffer: BUFFER,
@@ -183,34 +204,34 @@ pub mod dma1 {
// lisr low interrupt status register
// impl<CHANNEL> S5<CHANNEL> {
- impl S5<C4> {
+ impl super::Dma for S5<C4> {
// sXcr stream x configuration register
- pub(crate) fn cr(&mut self) -> &dma2::S5CR {
+ fn cr(&mut self) -> &dma2::S5CR {
unsafe { &(*DMA1::ptr()).s5cr }
}
// sXfcr stream x FIFO control register
- pub(crate) fn fcr(&mut self) -> &dma2::S5FCR {
+ fn fcr(&mut self) -> &dma2::S5FCR {
unsafe { &(*DMA1::ptr()).s5fcr }
}
// sXm0ar stream x memory 0 address register
- pub(crate) fn m0ar(&mut self) -> &dma2::S5M0AR {
+ fn m0ar(&mut self) -> &dma2::S5M0AR {
unsafe { &(*DMA1::ptr()).s5m0ar }
}
// sXm1ar stream x memory 0 address register
- pub(crate) fn m1ar(&mut self) -> &dma2::S5M1AR {
+ fn m1ar(&mut self) -> &dma2::S5M1AR {
unsafe { &(*DMA1::ptr()).s5m1ar }
}
// sXndtr stream x number of data register
- pub(crate) fn ndtr(&mut self) -> &dma2::S5NDTR {
+ fn ndtr(&mut self) -> &dma2::S5NDTR {
unsafe { &(*DMA1::ptr()).s5ndtr }
}
// sXpar stream x peripheral address register
- pub(crate) fn par(&mut self) -> &dma2::S5PAR {
+ fn par(&mut self) -> &dma2::S5PAR {
unsafe { &(*DMA1::ptr()).s5par }
}
}
diff --git a/src/serial.rs b/src/serial.rs
index e03a8d6..dad679f 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -13,7 +13,7 @@ use cast::u16;
use hal::serial;
use nb;
use stm32f4x::{USART1, USART2, USART6};
-use dma::{Static, Transfer, Usart1TxStream, R};
+use dma::{Dma, Static, Transfer, Usart1TxStream, R};
// usart2
use gpio::gpioa::{PA2, PA3};
@@ -250,18 +250,16 @@ macro_rules! hal {
where
A: Unsize<[u8]>,
B: Static<A>,
- S: Usart1TxStream<$USARTX>
+ S: Usart1TxStream<$USARTX> + Dma
{
- // // write!(dma1, "hi {}", 1);
- // let usart2 = self.0;
-
- // let buffer: &[u8] = buffer.borrow();
- // stream.ndtr()
- // .write(|w| unsafe { w.ndt().bits(u16(buffer.len()).unwrap()) });
- // dma1.s6par
- // .write(|w| unsafe { w.bits(&usart2.dr as *const _ as u32) });
- // dma1.s6m0ar
- // .write(|w| unsafe { w.bits(buffer.as_ptr() as u32) });
+ {
+ let buffer1 :&[u8] = buffer.borrow();
+ stream.ndtr()
+ .write(|w| unsafe { w.ndt().bits(u16(buffer1.len()).unwrap()) });
+ stream.par()
+ .write(|w| unsafe { w.bits(&(*$USARTX::ptr()).dr as *const _ as usize as u32) });
+ stream.m0ar()
+ .write(|w| unsafe { w.bits(buffer1.as_ptr() as u32) });
// dma1.s6cr.modify(|_, w| w.en().set_bit());
@@ -302,7 +300,7 @@ macro_rules! hal {
// .en()
// .set_bit()
// });
-
+ }
Transfer::r(buffer, stream, self)
}
--
GitLab