From 87a48ef2650187ce9d901f0e9fca2937b360f469 Mon Sep 17 00:00:00 2001
From: Per Lindgren <per.lindgren@ltu.se>
Date: Sun, 11 Feb 2018 07:58:17 +0100
Subject: [PATCH] dma tx kind of works
---
.gdbinit | 6 +++---
.vscode/launch.json | 24 ++++++++++++++++++++++++
Cargo.toml | 2 +-
src/dma.rs | 2 +-
src/serial.rs | 14 ++++++++++++++
5 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/.gdbinit b/.gdbinit
index b56176a..a9dd8b4 100644
--- a/.gdbinit
+++ b/.gdbinit
@@ -1,6 +1,6 @@
-target remote :3333
+# target remote :3333
# monitor reset init
-monitor arm semihosting enable
+# monitor arm semihosting enable
# send captured ITM to the file /tmp/itm.log
# (the microcontroller SWO pin must be connected to the programmer SWO pin)
@@ -13,4 +13,4 @@ monitor itm port 0 on
#load
#step
# monitor reset halt
-detach
+# detach
diff --git a/.vscode/launch.json b/.vscode/launch.json
index d91619d..9d29e47 100644
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@@ -82,5 +82,29 @@
],
"cwd": "${workspaceRoot}"
},
+ {
+ "type": "cortex-debug",
+ "request": "launch",
+ "servertype": "openocd",
+ "name": "Debug Microcontroller",
+ "executable": "./target/thumbv7em-none-eabihf/debug/examples/serial-dma-tx",
+ "configFiles": [
+ "interface/stlink.cfg",
+ "target/stm32f4x.cfg"
+ ],
+ "swoConfig": [
+ "enabled": "true",
+ "swoFrequency": "0",
+ "cpuFrequency": "0",
+ "ports": [
+ [
+ "number": "0",
+ "label": "0",
+ "format": "console",
+ ]
+ ]
+ ],
+ "cwd": "${workspaceRoot}"
+ }
]
}
\ No newline at end of file
diff --git a/Cargo.toml b/Cargo.toml
index f02a119..d6beaf6 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -23,7 +23,7 @@ branch = "svd2rust0.12"
default-features = false
version = "0.2.2"
-[dependencies.cortex-m-debug]
+[ dependencies.cortex-m-debug]
git = "https://gitlab.henriktjader.com/pln/cortex-m-debug.git"
version = "0.1.2"
branch = "cortex-m-4"
diff --git a/src/dma.rs b/src/dma.rs
index 1fda842..6e8a04e 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -309,7 +309,7 @@ pub mod dma1 {
}
asm::bkpt();
dma.hifcr.write(|w| w.ctcif6().set_bit());
- dma.s2cr.modify(|_, w| w.en().clear_bit());
+ dma.s6cr.modify(|_, w| w.en().clear_bit());
// TODO can we weaken this compiler barrier?
// NOTE(compiler_fence) operations on `buffer` should not be reordered
diff --git a/src/serial.rs b/src/serial.rs
index 08b1410..c37a132 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -137,6 +137,20 @@ macro_rules! hal {
.cr1
.write(|w| w.ue().set_bit().re().set_bit().te().set_bit());
+ // disable hardware flow control
+ // enable DMA TX and RX transfers
+
+ usart.cr3.write(|w| {
+ w.rtse()
+ .clear_bit()
+ .ctse()
+ .clear_bit()
+ .dmat()
+ .set_bit()
+ .dmar()
+ .set_bit()
+ });
+
Serial { usart, pins }
}
--
GitLab