diff --git a/.gdbinit b/.gdbinit
index b56176a11fcdaa14d4ab33eb8e53e8959d4bf3f5..a9dd8b4b0d9adf32965dfd6c0b01eee33ea53949 100644
--- a/.gdbinit
+++ b/.gdbinit
@@ -1,6 +1,6 @@
-target remote :3333
+# target remote :3333
 # monitor reset init
-monitor arm semihosting enable
+# monitor arm semihosting enable
 
 # send captured ITM to the file /tmp/itm.log
 # (the microcontroller SWO pin must be connected to the programmer SWO pin)
@@ -13,4 +13,4 @@ monitor itm port 0 on
 #load
 #step
 # monitor reset halt
-detach
+# detach
diff --git a/.vscode/launch.json b/.vscode/launch.json
index d91619dd3e9a36730443b4d4c5beaf17dd4db6d4..9d29e4797eae871d413c35b088b1a40c0a142219 100644
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@@ -82,5 +82,29 @@
             ],
             "cwd": "${workspaceRoot}"
         },
+        {
+            "type": "cortex-debug",
+            "request": "launch",
+            "servertype": "openocd",
+            "name": "Debug Microcontroller",
+            "executable": "./target/thumbv7em-none-eabihf/debug/examples/serial-dma-tx",
+            "configFiles": [
+                "interface/stlink.cfg",
+                "target/stm32f4x.cfg"
+            ],
+            "swoConfig": [
+                "enabled": "true",
+                "swoFrequency": "0",
+                "cpuFrequency": "0",
+                "ports": [
+                    [
+                        "number": "0",
+                        "label": "0",
+                        "format": "console",
+                    ]
+                ]
+            ],
+            "cwd": "${workspaceRoot}"
+        }
     ]
 }
\ No newline at end of file
diff --git a/Cargo.toml b/Cargo.toml
index f02a11947b9912c9fd39d39a06a30f1fc92d011d..d6beaf6274a62d2a962efa1fce53265d21813c08 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -23,7 +23,7 @@ branch = "svd2rust0.12"
 default-features = false
 version = "0.2.2"
 
-[dependencies.cortex-m-debug]
+[   dependencies.cortex-m-debug]
 git = "https://gitlab.henriktjader.com/pln/cortex-m-debug.git"
 version = "0.1.2"
 branch = "cortex-m-4"
diff --git a/src/dma.rs b/src/dma.rs
index 1fda842245e680031c152fe8b9569cc2b18f1bb0..6e8a04ec9d1b2d0d1e995157f400b37a7440216d 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -309,7 +309,7 @@ pub mod dma1 {
             }
             asm::bkpt();
             dma.hifcr.write(|w| w.ctcif6().set_bit());
-            dma.s2cr.modify(|_, w| w.en().clear_bit());
+            dma.s6cr.modify(|_, w| w.en().clear_bit());
 
             // TODO can we weaken this compiler barrier?
             // NOTE(compiler_fence) operations on `buffer` should not be reordered
diff --git a/src/serial.rs b/src/serial.rs
index 08b14105b652d213318476bbe26f37b4535ab565..c37a132d8d43088fd6ac06c531bbd76557a117f1 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -137,6 +137,20 @@ macro_rules! hal {
                         .cr1
                         .write(|w| w.ue().set_bit().re().set_bit().te().set_bit());
 
+                    // disable hardware flow control
+                    // enable DMA TX and RX transfers
+
+                    usart.cr3.write(|w| {
+                        w.rtse()
+                            .clear_bit()
+                            .ctse()
+                            .clear_bit()
+                            .dmat()
+                            .set_bit()
+                            .dmar()
+                            .set_bit()
+                    });
+
                     Serial { usart, pins }
                 }