From 5b1dfe924fea71c880a0524460656ebadcddbe9b Mon Sep 17 00:00:00 2001
From: Per Lindgren <per.lindgren@ltu.se>
Date: Wed, 7 Feb 2018 22:56:21 +0100
Subject: [PATCH] dma Stream 5
---
src/dma.rs | 56 +++++++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 47 insertions(+), 9 deletions(-)
diff --git a/src/dma.rs b/src/dma.rs
index 6b9e5e4..2a5bdc8 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -167,15 +167,53 @@ pub mod dma1 {
pub struct Streams(pub S4<C0>, pub S5<C0>);
- // impl {
- // pub fn listen(&mut self, event: Event) {
- // match event {
- // Event::HalfTransfer => self.ccr().modify(|_, w| w.htie().set_bit()),
- // Event::TransferComplete => {
- // self.ccr().modify(|_, w| w.tcie().set_bit())
- // }
- // }
- // }
+ impl<CHANNEL> S5<CHANNEL> {
+ pub fn listen(&mut self, event: Event) {
+ match event {
+ Event::HalfTransfer => (), // self.ccr().modify(|_, w| w.htie().set_bit()),
+ Event::TransferComplete => {
+ // self.ccr().modify(|_, w| w.tcie().set_bit())
+ }
+ }
+ }
+ }
+
+ // hifcr high interrupt flag clear register
+ // hisr high interrupt status register
+ // lifcr low interrupt flag clear register
+ // lisr low interrupt status register
+
+ impl<CHANNEL> S5<CHANNEL> {
+ // sXcr stream x configuration register
+ pub(crate) fn cr(&mut self) -> &dma2::S5CR {
+ unsafe { &(*DMA1::ptr()).s5cr }
+ }
+
+ // sXfcr stream x FIFO control register
+ pub(crate) fn fcr(&mut self) -> &dma2::S5FCR {
+ unsafe { &(*DMA1::ptr()).s5fcr }
+ }
+
+ // sXm0ar stream x memory 0 address register
+ pub(crate) fn m0ar(&mut self) -> &dma2::S5M0AR {
+ unsafe { &(*DMA1::ptr()).s5m0ar }
+ }
+
+ // sXm1ar stream x memory 0 address register
+ pub(crate) fn m1ar(&mut self) -> &dma2::S5M1AR {
+ unsafe { &(*DMA1::ptr()).s5m1ar }
+ }
+
+ // sXndtr stream x number of data register
+ pub(crate) fn ndtr(&mut self) -> &dma2::S5NDTR {
+ unsafe { &(*DMA1::ptr()).s5ndtr }
+ }
+
+ // s0par stream x peripheral address register
+ pub(crate) fn par(&mut self) -> &dma2::S5PAR {
+ unsafe { &(*DMA1::ptr()).s5par }
+ }
+ }
impl DmaExt for DMA1 {
type Streams = Streams;
--
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